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Hardware/software co-design of two-stage smart arrhythmia classifier based on multi-processor field programmable gate array system-on-chip

Cardiovascular diseases are the top cause of deaths in Malaysia since 2000. Arrhythmia is one of the precursors for cardiovascular disease that can be diagnosed via electrocardiogram (ECG). This research proposes an embedded multi-processor system-on-chip (MPSoC) architecture of in-house smart arrhy...

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Main Author: Ooi, Tze Kian
Format: Thesis
Language:English
Published: 2022
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/102694/1/OoiTzeKianMSKE2022.pdf.pdf
http://eprints.utm.my/id/eprint/102694/
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spelling my.utm.1026942023-09-18T03:56:59Z http://eprints.utm.my/id/eprint/102694/ Hardware/software co-design of two-stage smart arrhythmia classifier based on multi-processor field programmable gate array system-on-chip Ooi, Tze Kian TK Electrical engineering. Electronics Nuclear engineering Cardiovascular diseases are the top cause of deaths in Malaysia since 2000. Arrhythmia is one of the precursors for cardiovascular disease that can be diagnosed via electrocardiogram (ECG). This research proposes an embedded multi-processor system-on-chip (MPSoC) architecture of in-house smart arrhythmia classifier using Nordic NRF5282 microcontroller unit (MCU) and DBM Cyclone V system-on-chip SoC (DBM SoC). The MCU houses Bluetooth low energy (BLE) and a 64 MHz Cortex- M4 processor. DBM SoC consists offield programmable gate array (FPGA) with logic elements (LE) and a hardcore ARM Cortex A9 processor that can run at 800MHz frequency. Hardware accelerator for compute intensive Fast Fourier Transform (FFT) is implemented in FPGA using soft intellectual property (IP) provided by vendor Intel. The high-performance DBM SoC will execute arrhythmia classification while the MCU act as master processor that are able to power cycle DBM SoC. Bluetooth communication between MCU and external mobile phone allow user to control DBM SoC, ECG acquisition via mobile phone. Sanity verification, timing performance benchmarking and power measurement are performed on the proposed MPSoC system. Results show that the proposed MPSoC system is able to classify an ECG signal into 6 types of arrhythmias namely Atrial Fibrilaltion (AFib), Ventricular Tachycardia (VTach), premature atrial contractions (PAC), premature ventricular contractions (PVC), left bundle branch block (LBBB), right bundble branch block (RBBB) and normal sinus rhythm (NSR). The proposed system is also able to classify a 10 seconds ECG input data within 1 second, equivalent to real-time detection performance. Results also show the battery-powered MPSoC platform consumes less power in idle mode when the DBM SoC is turned off. The battery life is greatly improved which increase portability and usability as well. 2022 Thesis NonPeerReviewed application/pdf en http://eprints.utm.my/id/eprint/102694/1/OoiTzeKianMSKE2022.pdf.pdf Ooi, Tze Kian (2022) Hardware/software co-design of two-stage smart arrhythmia classifier based on multi-processor field programmable gate array system-on-chip. Masters thesis, Universiti Teknologi Malaysia. http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:149758
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Ooi, Tze Kian
Hardware/software co-design of two-stage smart arrhythmia classifier based on multi-processor field programmable gate array system-on-chip
description Cardiovascular diseases are the top cause of deaths in Malaysia since 2000. Arrhythmia is one of the precursors for cardiovascular disease that can be diagnosed via electrocardiogram (ECG). This research proposes an embedded multi-processor system-on-chip (MPSoC) architecture of in-house smart arrhythmia classifier using Nordic NRF5282 microcontroller unit (MCU) and DBM Cyclone V system-on-chip SoC (DBM SoC). The MCU houses Bluetooth low energy (BLE) and a 64 MHz Cortex- M4 processor. DBM SoC consists offield programmable gate array (FPGA) with logic elements (LE) and a hardcore ARM Cortex A9 processor that can run at 800MHz frequency. Hardware accelerator for compute intensive Fast Fourier Transform (FFT) is implemented in FPGA using soft intellectual property (IP) provided by vendor Intel. The high-performance DBM SoC will execute arrhythmia classification while the MCU act as master processor that are able to power cycle DBM SoC. Bluetooth communication between MCU and external mobile phone allow user to control DBM SoC, ECG acquisition via mobile phone. Sanity verification, timing performance benchmarking and power measurement are performed on the proposed MPSoC system. Results show that the proposed MPSoC system is able to classify an ECG signal into 6 types of arrhythmias namely Atrial Fibrilaltion (AFib), Ventricular Tachycardia (VTach), premature atrial contractions (PAC), premature ventricular contractions (PVC), left bundle branch block (LBBB), right bundble branch block (RBBB) and normal sinus rhythm (NSR). The proposed system is also able to classify a 10 seconds ECG input data within 1 second, equivalent to real-time detection performance. Results also show the battery-powered MPSoC platform consumes less power in idle mode when the DBM SoC is turned off. The battery life is greatly improved which increase portability and usability as well.
format Thesis
author Ooi, Tze Kian
author_facet Ooi, Tze Kian
author_sort Ooi, Tze Kian
title Hardware/software co-design of two-stage smart arrhythmia classifier based on multi-processor field programmable gate array system-on-chip
title_short Hardware/software co-design of two-stage smart arrhythmia classifier based on multi-processor field programmable gate array system-on-chip
title_full Hardware/software co-design of two-stage smart arrhythmia classifier based on multi-processor field programmable gate array system-on-chip
title_fullStr Hardware/software co-design of two-stage smart arrhythmia classifier based on multi-processor field programmable gate array system-on-chip
title_full_unstemmed Hardware/software co-design of two-stage smart arrhythmia classifier based on multi-processor field programmable gate array system-on-chip
title_sort hardware/software co-design of two-stage smart arrhythmia classifier based on multi-processor field programmable gate array system-on-chip
publishDate 2022
url http://eprints.utm.my/id/eprint/102694/1/OoiTzeKianMSKE2022.pdf.pdf
http://eprints.utm.my/id/eprint/102694/
http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:149758
_version_ 1778160767919456256
score 13.211869

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