Analysis of FPGA design methods using AN 8 BIT ALU
Field Programmable Logic Arrays (FPGAs) have been growing at a rapid rate in the past few years. FPGA is a type of logic chip that can be programmed which supports thousand of gates and provide flexibility and low cost which is suitable for implementing a prototype system. The existence of CA...
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| フォーマット: | 学位論文 |
| 言語: | English English English |
| 出版事項: |
2005
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| 主題: | |
| オンライン･アクセス: | http://eprints.uthm.edu.my/7753/1/24p%20ROSNAH%20MOHD%20ZIN.pdf http://eprints.uthm.edu.my/7753/2/ROSNAH%20MOHD%20ZIN%20COPYRIGHT%20DECLARATION.pdf http://eprints.uthm.edu.my/7753/3/ROSNAH%20MOHD%20ZIN%20WATERMARK.pdf http://eprints.uthm.edu.my/7753/ |
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| 要約: | Field Programmable Logic Arrays (FPGAs) have been growing at a rapid rate in
the past few years. FPGA is a type of logic chip that can be programmed which supports
thousand of gates and provide flexibility and low cost which is suitable for
implementing a prototype system. The existence of CA D software to support FPGAs has
grown in sophistication and it makes most user designs are now complete system and go
to production as an FPGA. This thesis will discuss on FPGA design style using an 8-bit
A L U as design hardware. Generally, the methods that used to implement the 8-bit AL U
are using schematic based entry and VHD L based entry. Implementation of 8-bit AL U
using VHD L includes a behavioral and structural description. The top level of design is
using a schematic based entry. Finally this thesis will discuss the methods that are used
in designing the 8-bit AL U in term of the flexibility, area consumption and timing
analysis. The analysis will give the user more understanding in designing digital system
using FPGA design style and give them a choice which depends on the design
requirements. |
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