Design of Gain Booster for Sample and Hold Stage of High Speed-Low Power Pipelined Analog-To-Digital Converter
This paper presents the full custom design of an operational transconductance amplifier (OTA) for the sample and hold (SHA) stage of a 10-bit 50-MS/s pipelined analog-to-digital converter (ADC) implemented in a TSMC 0.35μm CMOS process. The OTA chosen for this design is folded cascode with gain boos...
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| Format: | Article |
| Language: | English |
| Published: |
Penerbit UTeM
2013
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| Online Access: | http://eprints.utem.edu.my/id/eprint/9110/1/Design_of_Gain_Booster_for_Sample_and_Hold_Stage_of_High_Speed-Low_Power_Pipelined_Analog-To-Digital_Converter.pdf http://eprints.utem.edu.my/id/eprint/9110/ http://jtec.utem.edu.my/ |
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