Cover Image

On Defect Oriented Testing for Hybrid CMOS/memristor Memory

Hybrid CMOS/memristor memory (hybrid memory) technology is one of the emerging memory technologies potentially to replace conventional non-volatile flash memory. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques and reliabili...

Full description

Saved in:
Bibliographic Details
Main Authors: Haron, Nor Zaidi, Hamdioui, Said
Format: Conference or Workshop Item
Language:English
Published: 2011
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utem.edu.my/id/eprint/3758/1/NZBHaron_ATS11.pdf
http://eprints.utem.edu.my/id/eprint/3758/
http://www.computer.org/csdl
Tags: Add Tag
No Tags, Be the first to tag this record!
id my.utem.eprints.3758
record_format eprints
spelling my.utem.eprints.37582015-05-28T02:37:29Z http://eprints.utem.edu.my/id/eprint/3758/ On Defect Oriented Testing for Hybrid CMOS/memristor Memory Haron, Nor Zaidi Hamdioui, Said TK Electrical engineering. Electronics Nuclear engineering Hybrid CMOS/memristor memory (hybrid memory) technology is one of the emerging memory technologies potentially to replace conventional non-volatile flash memory. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques and reliability improvement. However, research on defect analysis for yield and quality improvement is still in its infancy stage. This paper presents a framework of defect oriented testing in hybrid memory based on electrical simulation. First, a classification and definition of defects is introduced. Second, a simulation model for defect injection and circuit simulation is proposed. Third, a case study to illustrate how the proposed approach can be used to analyze the defects and translate their electrical faulty behavior into fault models - in order to develop the appropriate tests and design for testability schemes - is provided. The simulation results show that in addition to the occurrence of conventional semiconductor memories faults, new unique faults take place, e.g., faults that cause the cell to hold an undefined state. These new unique faults require new test approaches (e.g., DfT) in order to be able to detect them. 2011-11-20 Conference or Workshop Item PeerReviewed application/pdf en http://eprints.utem.edu.my/id/eprint/3758/1/NZBHaron_ATS11.pdf Haron, Nor Zaidi and Hamdioui, Said (2011) On Defect Oriented Testing for Hybrid CMOS/memristor Memory. In: Asian Test Symposium 2011, 20-23 November 2011, New Delhi. http://www.computer.org/csdl
institution Universiti Teknikal Malaysia Melaka
building UTEM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknikal Malaysia Melaka
content_source UTEM Institutional Repository
url_provider http://eprints.utem.edu.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Haron, Nor Zaidi
Hamdioui, Said
On Defect Oriented Testing for Hybrid CMOS/memristor Memory
description Hybrid CMOS/memristor memory (hybrid memory) technology is one of the emerging memory technologies potentially to replace conventional non-volatile flash memory. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques and reliability improvement. However, research on defect analysis for yield and quality improvement is still in its infancy stage. This paper presents a framework of defect oriented testing in hybrid memory based on electrical simulation. First, a classification and definition of defects is introduced. Second, a simulation model for defect injection and circuit simulation is proposed. Third, a case study to illustrate how the proposed approach can be used to analyze the defects and translate their electrical faulty behavior into fault models - in order to develop the appropriate tests and design for testability schemes - is provided. The simulation results show that in addition to the occurrence of conventional semiconductor memories faults, new unique faults take place, e.g., faults that cause the cell to hold an undefined state. These new unique faults require new test approaches (e.g., DfT) in order to be able to detect them.
format Conference or Workshop Item
author Haron, Nor Zaidi
Hamdioui, Said
author_facet Haron, Nor Zaidi
Hamdioui, Said
author_sort Haron, Nor Zaidi
title On Defect Oriented Testing for Hybrid CMOS/memristor Memory
title_short On Defect Oriented Testing for Hybrid CMOS/memristor Memory
title_full On Defect Oriented Testing for Hybrid CMOS/memristor Memory
title_fullStr On Defect Oriented Testing for Hybrid CMOS/memristor Memory
title_full_unstemmed On Defect Oriented Testing for Hybrid CMOS/memristor Memory
title_sort on defect oriented testing for hybrid cmos/memristor memory
publishDate 2011
url http://eprints.utem.edu.my/id/eprint/3758/1/NZBHaron_ATS11.pdf
http://eprints.utem.edu.my/id/eprint/3758/
http://www.computer.org/csdl
_version_ 1665905260959367168
score 13.211869

Similar Items