Routing density analysis of area-efficient ring oscillator physically unclonable functions
The research into ring oscillator physically unclonable functions (RO-PUF) continues to expand due to its simple structure, ease of generating responses, and its promises of primitive security. However, a substantial study has yet to be carried out in developing designs of the FPGA-based RO-PUF, whi...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2021
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| Online Access: | http://eprints.utem.edu.my/id/eprint/25933/2/ROUTING%20DENSITY%20ANALYSIS%20OF%20AREA-EFFICIENT%20RING%20OSCILLATOR%20PHYSICALLY%20UNCLONABLE%20FUNCTIONS.PDF http://eprints.utem.edu.my/id/eprint/25933/ https://www.mdpi.com/2076-3417/11/20/9730 https://doi.org/10.3390/app11209730 |
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| Summary: | The research into ring oscillator physically unclonable functions (RO-PUF) continues to expand due to its simple structure, ease of generating responses, and its promises of primitive security. However, a substantial study has yet to be carried out in developing designs of the FPGA-based RO-PUF, which effectively balances performance and area efficiency. This work proposes a modified RO-PUF where the ring oscillators are connected directly to the counters. The proposed RO-PUF requires fewer RO than the conventional structure since this work utilizes the direct pulse count
method. This work aims to seek the ideal routing density of ROs to improve uniqueness. For this purpose, five logic arrangements of a wide range of routing densities of ROs were tested. Upon implementation onto the FPGA chip, the routing density of ROs are varied significantly in terms of wire utilization (higher than 25%) and routing hotspots (higher than 80%). The best uniqueness attained was 52.71%, while the highest reliability was 99.51%. This study improves the uniqueness by 2% subsequent to the application of scenarios to consider ROs with a narrow range of routing density.
The best range of wire utilization and routing hotspots of individual RO in this work is 3–5% and 20–50%, respectively. The performance metrics (uniqueness and reliability) of the proposed RO-PUF are much better than existing works using a similar FPGA platform (Altera), and it is as good as the recent RO-PUFs realized on Xilinx. Additionally, this work estimates the minimum runtimes to reduce error and response bit-flip of RO-PUF |
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