A Review Paper On Memory Fault Models And Test Algorithms
Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requireme...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Institute of Advanced Engineering and Science
2021
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| Online Access: | http://eprints.utem.edu.my/id/eprint/25762/2/2021_A%20REVIEW%20PAPER%20ON%20MEMORY%20FAULT%20MODELS%20AND%20TEST%20ALGORITHMS.PDF http://eprints.utem.edu.my/id/eprint/25762/ https://www.beei.org/index.php/EEI/article/view/3048/2409 |
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