Design And Analysis Of Cmos Based RFIC Voltage Controlled Oscillator (VCO) For 1.9GHz Range CDMA Applications
The objective of this paper is to present the Design and Analysis of CMOS Based RFIC Voltage Controlled Oscillator (VCO) for 1.9GHz Range for CDMA Application. The topology used to realize the oscillator is the Cross coupled differential LC tank negative trans-conductance voltage controlled os...
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| Main Author: | |
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| Format: | Monograph |
| Language: | English |
| Published: |
Universiti Sains Malaysia
2005
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| Subjects: | |
| Online Access: | http://eprints.usm.my/57601/1/Design%20And%20Analysis%20Of%20Cmos%20Based%20RFIC%20Voltage%20Controlled%20Oscillator%20%28VCO%29%20For%201.9GHz%20Range%20CDMA%20Applications_Lee%20Jen%20Huei.pdf http://eprints.usm.my/57601/ |
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| Summary: | The objective of this paper is to present the Design and Analysis of CMOS Based RFIC
Voltage Controlled Oscillator (VCO) for 1.9GHz Range for CDMA Application. The
topology used to realize the oscillator is the Cross coupled differential LC tank negative
trans-conductance voltage controlled oscillator. The design process begins from the
choice of topology. After a topology is chosen, then the targeted specification is set. The
circuit is simulated and optimized to meet the specifications. This is done in the
schematic and simulation entry. After the simulation results are satisfied, and then the
layout of the circuit is drawn. In the layout stage, design rules check (DRC) should
always performed to make sure the layout follow the design rules. After DRC checking,
the layout versus schematic (LVS) is performed to compare between schematic net list
file and layout net list file. The final stage will be the additional of the bond pad into the
layout. In chapter 1 of this paper, an introduction to transceiver architecture and Voltage
controlled oscillator is given. The various topology described in the previous published
paper to implement a Voltage Controlled Oscillator is compared between each other in
Chapter 2. In chapter 3, the analysis of the Cross coupled differential LC tank negative
trans-conductance topology used in the design of this paper is described. Chapter 4
discusses about the Phase Noise of the oscillator. The designed circuit is simulated using
Cadence CAD tools and the design kit is supplied by Silterra Malaysia Sdn. Bhd
(Silterra RF design kit, version 180804). The simulation results analysis are shown in
chapter 5. The layout process is described in chapter 6 and finally chapter 7 gives the
conclusion of the project. |
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