An Efficient Energy Aware Adaptive System-On-Chip Architecture For Real-Time Video Analytics
The video analytics applications which are mostly running on embedded devices have become prevalent in today’s life. This proliferation has necessitated the development of System-on-Chips (SoC) to perform utmost processing in a single chip rather than discrete components. Embedded vision is bound...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2016
|
| Subjects: | |
| Online Access: | http://eprints.usm.my/45827/1/An%20Efficient%20Energy%20Aware%20Adaptive%20System-On-Chip%20Architecture%20For%20Real-Time%20Video%20Analytics.pdf http://eprints.usm.my/45827/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | The video analytics applications which are mostly running on embedded devices have
become prevalent in today’s life. This proliferation has necessitated the development
of System-on-Chips (SoC) to perform utmost processing in a single chip rather than
discrete components. Embedded vision is bounded by stringent requirements, namely
real-time performance, limited energy, and Adaptivity to cope with the standards evolution.
Additionally, to design such complex SoCs, particularly in Zynq All Programmable
SoC, the traditional hardware/software codesign approaches, which rely
on software profiling to perform the hardware/software partitioning, have fallen short
of achieving this task because profiling cannot predict the performance of application
on hardware, thus, a model that relates the application characteristics to the platform
performance is inevitable. Delivering real-time performance for the fast-growing video
resolutions while maintaining the architecture flexibility is non-viable on processors,
Graphic Processing Unit, Digital Signal Processor, and Application Specific Integrated
Circuit. Furthermore, with semiconductor technology scaling, increased power dissipation
is expected; whereas, the battery capacity is not expected to increase significantly.
A Performance model for Zynq is developed using analytical method and used
in hardware/software codesign to facilitate algorithms mapping to hardware. Afterwards,
an SoC for real-time video analytics is realized on Zynq using Harris corner
detection algorithm. A careful analysis of the algorithm and efficient utilization of
Zynq resources results in highly parallelized and pipelined architecture outperforms
the state-of-the-art. Running on a developed energy-aware adaptive SoC and utilizing
dynamic partial reconfiguration, a context-aware configuration scheduler adheres to
operating context and trades off between video resolution and energy consumption to
sustain the uttermost operation time while delivering real-time performance. A realtime
corners detection at 79.8, 176.9, and 504.2 frame per second for HD1080, HD720,
and VGA, respectively, is achieved which outperform the state-of-the-art for HD720
by 31 times and for VGA by 3.5 times. The scheduler configures, at run-time, the
appropriate hardware that satisfies the operating context and user-defined constraints
among the accelerators that are developed for HD1080, HD720, and VGA video standards.
The self-adaptive method achieves 1.77 times longer operation time than a
parametrized IP core for the same battery capacity, with negligible reconfiguration energy
overhead. A marginal effect of reconfiguration time overhead is observed, for
instance, only two video frames are dropped for HD1080p60 during the reconfiguration.
Facilitating the design process by using analytical modeling, and the efficient
utilization of Zynq resources along with self-adaptivity results in an efficient energyaware
SoC that provides real-time performance for video analytics. |
|---|