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Enhancement Of Methodology And Definition For Serial Protocol Electrical Specification Compatibility For Non-Compliant Fpga

A new methodology and definition for a clearer compatibility for middle-range and low-end Field Programmable Gate Array (FPGA) transceiver is presented in this research. It has been a big challenge to balance between cost and performance in order to meet the full industrial protocol specification fo...

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Main Author: Tan , Shwu Fei
Format: Thesis
Language:English
Published: 2014
Subjects:
TK Electrical Engineering. Electronics. Nuclear Engineering
Online Access:http://eprints.usm.my/40919/1/TAN_SHWU_FEI_24_pages.pdf
http://eprints.usm.my/40919/
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spelling my.usm.eprints.40919 http://eprints.usm.my/40919/ Enhancement Of Methodology And Definition For Serial Protocol Electrical Specification Compatibility For Non-Compliant Fpga Tan , Shwu Fei TK Electrical Engineering. Electronics. Nuclear Engineering A new methodology and definition for a clearer compatibility for middle-range and low-end Field Programmable Gate Array (FPGA) transceiver is presented in this research. It has been a big challenge to balance between cost and performance in order to meet the full industrial protocol specification for middle-range and low-end FPGA. When the products are not able to achieve full protocol specification, the company will still market these products and claim that they are compatible. With this kind of situation, there are no guidelines can be followed; hence, users will not have confidence to design the product. In this research, a clearer compatible specification is obtained to provide channel loss requirement by extracting the timing margin at different test points. The research also ensures that quantifiable margin is allocated when compatible specification is defined. The middle-range FPGA that used in this research is Arria V GT device to define the new compatible specification with reference to IEEE 10GBASE-KR protocol where the compatible specification is used for board-based 10Gbps applications. The methodology used is by extracting the timing margin and find out the channel loss from 3 different test points which include Scenario 1) Transmitter is Arria V GT; Receiver is Compliant Receiver, Scenario 2) Transmitter and Receiver are from Arria V GT and Scenario 3) Transmitter is Compliant Transmitter; Receiver is from Arria V GT. 16-ps of timing margin is obtained from the research, while the channel loss for Scenario 1 is -16dB, Scenario 2 is -12dB and Scenario 3 is -17dB with error-free transfer for BER10-12 . 2014 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/40919/1/TAN_SHWU_FEI_24_pages.pdf Tan , Shwu Fei (2014) Enhancement Of Methodology And Definition For Serial Protocol Electrical Specification Compatibility For Non-Compliant Fpga. Masters thesis, Universiti Sains Malaysia.
institution Universiti Sains Malaysia
building Hamzah Sendut Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Sains Malaysia
content_source USM Institutional Repository
url_provider http://eprints.usm.my/
language English
topic TK Electrical Engineering. Electronics. Nuclear Engineering
spellingShingle TK Electrical Engineering. Electronics. Nuclear Engineering
Tan , Shwu Fei
Enhancement Of Methodology And Definition For Serial Protocol Electrical Specification Compatibility For Non-Compliant Fpga
description A new methodology and definition for a clearer compatibility for middle-range and low-end Field Programmable Gate Array (FPGA) transceiver is presented in this research. It has been a big challenge to balance between cost and performance in order to meet the full industrial protocol specification for middle-range and low-end FPGA. When the products are not able to achieve full protocol specification, the company will still market these products and claim that they are compatible. With this kind of situation, there are no guidelines can be followed; hence, users will not have confidence to design the product. In this research, a clearer compatible specification is obtained to provide channel loss requirement by extracting the timing margin at different test points. The research also ensures that quantifiable margin is allocated when compatible specification is defined. The middle-range FPGA that used in this research is Arria V GT device to define the new compatible specification with reference to IEEE 10GBASE-KR protocol where the compatible specification is used for board-based 10Gbps applications. The methodology used is by extracting the timing margin and find out the channel loss from 3 different test points which include Scenario 1) Transmitter is Arria V GT; Receiver is Compliant Receiver, Scenario 2) Transmitter and Receiver are from Arria V GT and Scenario 3) Transmitter is Compliant Transmitter; Receiver is from Arria V GT. 16-ps of timing margin is obtained from the research, while the channel loss for Scenario 1 is -16dB, Scenario 2 is -12dB and Scenario 3 is -17dB with error-free transfer for BER10-12 .
format Thesis
author Tan , Shwu Fei
author_facet Tan , Shwu Fei
author_sort Tan , Shwu Fei
title Enhancement Of Methodology And Definition For Serial Protocol Electrical Specification Compatibility For Non-Compliant Fpga
title_short Enhancement Of Methodology And Definition For Serial Protocol Electrical Specification Compatibility For Non-Compliant Fpga
title_full Enhancement Of Methodology And Definition For Serial Protocol Electrical Specification Compatibility For Non-Compliant Fpga
title_fullStr Enhancement Of Methodology And Definition For Serial Protocol Electrical Specification Compatibility For Non-Compliant Fpga
title_full_unstemmed Enhancement Of Methodology And Definition For Serial Protocol Electrical Specification Compatibility For Non-Compliant Fpga
title_sort enhancement of methodology and definition for serial protocol electrical specification compatibility for non-compliant fpga
publishDate 2014
url http://eprints.usm.my/40919/1/TAN_SHWU_FEI_24_pages.pdf
http://eprints.usm.my/40919/
_version_ 1643710075869593600
score 13.211869

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