Generating power-optimal standard cell library specification using neural network technique
In VLSI semi-custom design approach, power-optimal standard cell library selection for a given block design requires time-consuming iterative processes. This paper presents a framework to select a standard cell library that can result in near-optimal power while satisfying targeted frequency. The fr...
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| 主要な著者: | , , , , , , |
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| フォーマット: | Conference or Workshop Item |
| 言語: | English |
| 出版事項: |
IEEE
2017
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| オンライン･アクセス: | http://psasir.upm.edu.my/id/eprint/68267/1/Generating%20power-optimal%20standard%20cell%20library%20specification%20using%20neural%20network%20technique.pdf http://psasir.upm.edu.my/id/eprint/68267/ |
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| 要約: | In VLSI semi-custom design approach, power-optimal standard cell library selection for a given block design requires time-consuming iterative processes. This paper presents a framework to select a standard cell library that can result in near-optimal power while satisfying targeted frequency. The framework relies on neural network model to quickly predict the total power of a block design associated with a given standard cell library in order to speed up the synthesis process. The experimental result based on various synthesized benchmark circuits demonstrated the effectiveness of proposed framework for near-optimal standard cell library specification. |
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