The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model
Purpose – This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD). Design/methodology/approach – The code uses a generator matrix designed for four-state space time trellis code (STTC) that use...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Emerald Group Publishing
2016
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| Online Access: | http://psasir.upm.edu.my/id/eprint/52962/1/The%20design%20of%20viterbi%20decoder%20for%20low%20power%20consumption%20space%20time%20trellis%20code%20without%20adder%20architecture%20using%20RTL%20model.pdf http://psasir.upm.edu.my/id/eprint/52962/ http://www.multi-science.co.uk/wje.htm |
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