Area efficient test circuit for library standard cell qualification
High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load c...
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| Main Authors: | , , , , |
|---|---|
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2015
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| Online Access: | http://psasir.upm.edu.my/id/eprint/2848/1/Area%20efficient%20test%20circuit%20for%20library%20standard%20cell%20qualification.pdf http://psasir.upm.edu.my/id/eprint/2848/ |
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