Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage
This paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time. Taguchi method determines the setting of process param...
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| Main Authors: | , , , , , , , |
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| 格式: | Article |
| 出版: |
2017
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| 在線閱讀: | http://dspace.uniten.edu.my:80/jspui/handle/123456789/5240 |
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