Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method

In this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectr...

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Main Authors: Afifah Maheran, A.H., Menon, P.S., Ahmad, I., Shaari, S.
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Published: 2017
Online Access:http://dspace.uniten.edu.my:80/jspui/handle/123456789/5207
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spelling my.uniten.dspace-52072020-09-10T04:36:02Z Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method Afifah Maheran, A.H. Menon, P.S. Ahmad, I. Shaari, S. In this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectric layer to replace the traditional silicon dioxide SiO2 and tungsten silicide (WSix) was used as a metal gate to replace polysilicon. The device's fabrication and electrical characterization were executed using ATHENA and ATLAS modules from Silvaco International. Taguchi's Power of Three Series L9 orthogonal array was used to optimize the device process parameters and to finally predict the best process parameter combination to obtain the minimum leakage current (ILEAK) using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The optimization resulted in the attainment of the lowest ILEAK mean value of 0.25759 nA/μm which is in accordance to the predicted value given in the International Technology Roadmap for Semiconductors (ITRS) 2011. © 2014 Penerbit UTM Press. All rights reserved. 2017-11-15T02:56:35Z 2017-11-15T02:56:35Z 2014 http://dspace.uniten.edu.my:80/jspui/handle/123456789/5207
institution Universiti Tenaga Nasional
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country Malaysia
content_provider Universiti Tenaga Nasional
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description In this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectric layer to replace the traditional silicon dioxide SiO2 and tungsten silicide (WSix) was used as a metal gate to replace polysilicon. The device's fabrication and electrical characterization were executed using ATHENA and ATLAS modules from Silvaco International. Taguchi's Power of Three Series L9 orthogonal array was used to optimize the device process parameters and to finally predict the best process parameter combination to obtain the minimum leakage current (ILEAK) using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The optimization resulted in the attainment of the lowest ILEAK mean value of 0.25759 nA/μm which is in accordance to the predicted value given in the International Technology Roadmap for Semiconductors (ITRS) 2011. © 2014 Penerbit UTM Press. All rights reserved.
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author Afifah Maheran, A.H.
Menon, P.S.
Ahmad, I.
Shaari, S.
spellingShingle Afifah Maheran, A.H.
Menon, P.S.
Ahmad, I.
Shaari, S.
Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method
author_facet Afifah Maheran, A.H.
Menon, P.S.
Ahmad, I.
Shaari, S.
author_sort Afifah Maheran, A.H.
title Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method
title_short Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method
title_full Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method
title_fullStr Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method
title_full_unstemmed Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method
title_sort optimisation of process parameters for lower leakage current in 22 nm n-type mosfet device using taguchi method
publishDate 2017
url http://dspace.uniten.edu.my:80/jspui/handle/123456789/5207
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score 13.222552