Staff View: Characterization of fabrication process noises for 32nm NMOS devices

Characterization of fabrication process noises for 32nm NMOS devices

This paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is...

Full description

Saved in:

Bibliographic Details
Main Authors:	Elgomati H.A., Majlis B.Y., Ahmad I., Ziad T.
Other Authors:	36536722700
Format:	Conference Paper
Published:	2023
Subjects:	Fabrication MOS devices Semiconductor growth Silicides Taguchi methods Threshold voltage Annealing temperatures Degree of noise Diffusion temperature Fabrication process Nanometer device NMOS devices NMOS transistors Optimum fabrication Sacrificial oxide Transistors
Tags:	Add Tag No Tags, Be the first to tag this record!

id	my.uniten.dspace-30628
record_format	dspace
spelling	my.uniten.dspace-306282024-04-18T10:27:10Z Characterization of fabrication process noises for 32nm NMOS devices Elgomati H.A. Majlis B.Y. Ahmad I. Ziad T. 36536722700 6603071546 12792216600 36538607500 Fabrication MOS devices Semiconductor growth Silicides Taguchi methods Threshold voltage Annealing temperatures Degree of noise Diffusion temperature Fabrication process Nanometer device NMOS devices NMOS transistors Optimum fabrication Sacrificial oxide Transistors This paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is �1�C variation in sacrificial oxide layer growth by diffusion temperature and also silicide compress annealing temperature. In this project, a working 32 NMOS transistor fabrication is used. By increasing the sacrificial oxide layer diffusion temperature from 900�C to 901�C, the reference 32nm NMOS transistor threshold voltage (VTH) jumps from 0.1181V to 0.1394V, while leakage current drops from 0.111mA/um to 0.109 mA/um. By decreasing the silicide compress temperature from 910�C to 909�C, threshold voltage increase slightly from 0.118053V to 0.118068V, This shows a very different in magnitude of effect from same degree of noise introduce to the fabrication process. � 2010 IEEE. Final 2023-12-29T07:50:29Z 2023-12-29T07:50:29Z 2010 Conference Paper 10.1109/SMELEC.2010.5549581 2-s2.0-77957602886 https://www.scopus.com/inward/record.uri?eid=2-s2.0-77957602886&doi=10.1109%2fSMELEC.2010.5549581&partnerID=40&md5=e340f7f826382926c67bac76123e58b5 https://irepository.uniten.edu.my/handle/123456789/30628 5549581 252 255 Scopus
institution	Universiti Tenaga Nasional
building	UNITEN Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Tenaga Nasional
content_source	UNITEN Institutional Repository
url_provider	http://dspace.uniten.edu.my/
topic	Fabrication MOS devices Semiconductor growth Silicides Taguchi methods Threshold voltage Annealing temperatures Degree of noise Diffusion temperature Fabrication process Nanometer device NMOS devices NMOS transistors Optimum fabrication Sacrificial oxide Transistors
spellingShingle	Fabrication MOS devices Semiconductor growth Silicides Taguchi methods Threshold voltage Annealing temperatures Degree of noise Diffusion temperature Fabrication process Nanometer device NMOS devices NMOS transistors Optimum fabrication Sacrificial oxide Transistors Elgomati H.A. Majlis B.Y. Ahmad I. Ziad T. Characterization of fabrication process noises for 32nm NMOS devices
description	This paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is �1�C variation in sacrificial oxide layer growth by diffusion temperature and also silicide compress annealing temperature. In this project, a working 32 NMOS transistor fabrication is used. By increasing the sacrificial oxide layer diffusion temperature from 900�C to 901�C, the reference 32nm NMOS transistor threshold voltage (VTH) jumps from 0.1181V to 0.1394V, while leakage current drops from 0.111mA/um to 0.109 mA/um. By decreasing the silicide compress temperature from 910�C to 909�C, threshold voltage increase slightly from 0.118053V to 0.118068V, This shows a very different in magnitude of effect from same degree of noise introduce to the fabrication process. � 2010 IEEE.
author2	36536722700
author_facet	36536722700 Elgomati H.A. Majlis B.Y. Ahmad I. Ziad T.
format	Conference Paper
author	Elgomati H.A. Majlis B.Y. Ahmad I. Ziad T.
author_sort	Elgomati H.A.
title	Characterization of fabrication process noises for 32nm NMOS devices
title_short	Characterization of fabrication process noises for 32nm NMOS devices
title_full	Characterization of fabrication process noises for 32nm NMOS devices
title_fullStr	Characterization of fabrication process noises for 32nm NMOS devices
title_full_unstemmed	Characterization of fabrication process noises for 32nm NMOS devices
title_sort	characterization of fabrication process noises for 32nm nmos devices
publishDate	2023
_version_	1806425835123507200
score	13.222552

Characterization of fabrication process noises for 32nm NMOS devices

Similar Items