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Application of Taguchi method in the optimization of process variation for 32nm CMOS technology

In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determi...

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Main Authors:	Elgomati H.A., Majlis B.Y., Ahmad I., Salehuddin F., Hamid F.A., Zaharim A., Apte P.R.
Other Authors:	36536722700
Format:	Article
Published:	2023
Subjects:	Compensation implantation HALO S/D implantation Silicon MOSFET 32nm Taguchi method Threshold voltage
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id	my.uniten.dspace-29610
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spelling	my.uniten.dspace-296102023-12-28T15:05:48Z Application of Taguchi method in the optimization of process variation for 32nm CMOS technology Elgomati H.A. Majlis B.Y. Ahmad I. Salehuddin F. Hamid F.A. Zaharim A. Apte P.R. 36536722700 6603071546 12792216600 36239165300 6603573875 15119466900 55725529100 Compensation implantation HALO S/D implantation Silicon MOSFET 32nm Taguchi method Threshold voltage In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determined by Taguchi method in experimental design. The influence of the main process parameters on threshold voltage were determined using analysis of variance (ANOVA). The fabrication processes of the transistor were performed by a simulator namely ATHENA. The electrical characterization of the device was done by the a simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing process parameters. The other two parameter used in this experiments were Source/Drain (S/D) implantation dose and, silicide annealing temperature Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of 0.10308V and -0.10319V for NMOS and PMOS respectively. As conclusion, by utilizing Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.103V that is well within ITRS prediction for 32nm transistor. Final 2023-12-28T07:05:48Z 2023-12-28T07:05:48Z 2011 Article 2-s2.0-79960517117 https://www.scopus.com/inward/record.uri?eid=2-s2.0-79960517117&partnerID=40&md5=b54a71cbe95e2ac50dbefd10daf00887 https://irepository.uniten.edu.my/handle/123456789/29610 5 7 346 355 Scopus
institution	Universiti Tenaga Nasional
building	UNITEN Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Tenaga Nasional
content_source	UNITEN Institutional Repository
url_provider	http://dspace.uniten.edu.my/
topic	Compensation implantation HALO S/D implantation Silicon MOSFET 32nm Taguchi method Threshold voltage
spellingShingle	Compensation implantation HALO S/D implantation Silicon MOSFET 32nm Taguchi method Threshold voltage Elgomati H.A. Majlis B.Y. Ahmad I. Salehuddin F. Hamid F.A. Zaharim A. Apte P.R. Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
description	In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determined by Taguchi method in experimental design. The influence of the main process parameters on threshold voltage were determined using analysis of variance (ANOVA). The fabrication processes of the transistor were performed by a simulator namely ATHENA. The electrical characterization of the device was done by the a simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing process parameters. The other two parameter used in this experiments were Source/Drain (S/D) implantation dose and, silicide annealing temperature Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of 0.10308V and -0.10319V for NMOS and PMOS respectively. As conclusion, by utilizing Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.103V that is well within ITRS prediction for 32nm transistor.
author2	36536722700
author_facet	36536722700 Elgomati H.A. Majlis B.Y. Ahmad I. Salehuddin F. Hamid F.A. Zaharim A. Apte P.R.
format	Article
author	Elgomati H.A. Majlis B.Y. Ahmad I. Salehuddin F. Hamid F.A. Zaharim A. Apte P.R.
author_sort	Elgomati H.A.
title	Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
title_short	Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
title_full	Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
title_fullStr	Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
title_full_unstemmed	Application of Taguchi method in the optimization of process variation for 32nm CMOS technology
title_sort	application of taguchi method in the optimization of process variation for 32nm cmos technology
publishDate	2023
_version_	1806425519078506496
score	13.222552

Application of Taguchi method in the optimization of process variation for 32nm CMOS technology

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