Staff View: Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage

Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage

This paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time. Taguchi method determines the setting of process param...

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Main Authors:	Elgomati H.A., Majlis B.Y., Ahmad I., Salehuddin F., Hamid F.A., Zaharim A., Mohamad T.Z., Apte P.R.
Other Authors:	36536722700
Format:	Article
Published:	2023
Subjects:	32 nm PMOS device Compensation implantation HALO S/D implantation Taguchi's method Threshold voltage
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spelling	my.uniten.dspace-296072023-12-28T15:05:48Z Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage Elgomati H.A. Majlis B.Y. Ahmad I. Salehuddin F. Hamid F.A. Zaharim A. Mohamad T.Z. Apte P.R. 36536722700 6603071546 12792216600 36239165300 6603573875 15119466900 53064272300 55725529100 32 nm PMOS device Compensation implantation HALO S/D implantation Taguchi's method Threshold voltage This paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time. Taguchi method determines the setting of process parameters in experimental design while analysis of variance (ANOVA) determines the influence of the main process parameters on threshold voltage. The fabrication processes of the transistor were performed by ATHENA fabrication simulator, while the electrical characterization of the device was done by an ATLAS characterization simulator. These two simulators were combined and the results were analyzed by Taguchi's method in order to aid in design and optimizing process parameters. Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of -0.10319 V is achieved for a 32 nm PMOS transistor. In conclusion, by utilizing Taguchi's method to analyze the effect of process parameters, we can adjust threshold voltage (VTH) for PMOS to a stable value of -0.10319 V that is well within ITRS prediction for a 32 nm PMOS transistor. � 2011 Academic Journals. Final 2023-12-28T07:05:48Z 2023-12-28T07:05:48Z 2011 Article 2-s2.0-80053909219 https://www.scopus.com/inward/record.uri?eid=2-s2.0-80053909219&partnerID=40&md5=3b1b0cbdd22ba4d8b2dcd6e0798b7821 https://irepository.uniten.edu.my/handle/123456789/29607 6 10 2372 2379 Scopus
institution	Universiti Tenaga Nasional
building	UNITEN Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Tenaga Nasional
content_source	UNITEN Institutional Repository
url_provider	http://dspace.uniten.edu.my/
topic	32 nm PMOS device Compensation implantation HALO S/D implantation Taguchi's method Threshold voltage
spellingShingle	32 nm PMOS device Compensation implantation HALO S/D implantation Taguchi's method Threshold voltage Elgomati H.A. Majlis B.Y. Ahmad I. Salehuddin F. Hamid F.A. Zaharim A. Mohamad T.Z. Apte P.R. Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage
description	This paper explains our investigation of the effect on 32 nm PMOS device threshold voltage (VTH) by four process parameters, namely HALO implantation, Source/Drain (S/D) implantation dose, compensation implantations, and silicide annealing time. Taguchi method determines the setting of process parameters in experimental design while analysis of variance (ANOVA) determines the influence of the main process parameters on threshold voltage. The fabrication processes of the transistor were performed by ATHENA fabrication simulator, while the electrical characterization of the device was done by an ATLAS characterization simulator. These two simulators were combined and the results were analyzed by Taguchi's method in order to aid in design and optimizing process parameters. Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of -0.10319 V is achieved for a 32 nm PMOS transistor. In conclusion, by utilizing Taguchi's method to analyze the effect of process parameters, we can adjust threshold voltage (VTH) for PMOS to a stable value of -0.10319 V that is well within ITRS prediction for a 32 nm PMOS transistor. � 2011 Academic Journals.
author2	36536722700
author_facet	36536722700 Elgomati H.A. Majlis B.Y. Ahmad I. Salehuddin F. Hamid F.A. Zaharim A. Mohamad T.Z. Apte P.R.
format	Article
author	Elgomati H.A. Majlis B.Y. Ahmad I. Salehuddin F. Hamid F.A. Zaharim A. Mohamad T.Z. Apte P.R.
author_sort	Elgomati H.A.
title	Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage
title_short	Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage
title_full	Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage
title_fullStr	Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage
title_full_unstemmed	Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage
title_sort	statistical optimization for process parameters to reduce variability of 32 nm pmos transistor threshold voltage
publishDate	2023
_version_	1806424204713656320
score	13.222552

Statistical optimization for process parameters to reduce variability of 32 nm PMOS transistor threshold voltage

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