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Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method

This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilic...

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Main Authors:	Elgomati H.A., Majlis B.Y., Ahmad I.
Other Authors:	36536722700
Format:	Conference paper
Published:	2023
Subjects:	Compensation Implantation HALO S/D implantation Silicon MOSFET 32nm Taguchi L18 Taguchi Method Threshold voltage
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id	my.uniten.dspace-29472
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spelling	my.uniten.dspace-294722023-12-28T14:30:10Z Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method Elgomati H.A. Majlis B.Y. Ahmad I. 36536722700 6603071546 12792216600 Compensation Implantation HALO S/D implantation Silicon MOSFET 32nm Taguchi L18 Taguchi Method Threshold voltage This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilicon thickness and silicide annealing time. The setting of process parameters were determined by Taguchi method L18 experimental design. From there, the level of importance of each of the process parameters on threshold voltage was determined using analysis of variance (ANOVA). Transistor fabrication was performed by using Silvaco ATHENA module. Silvaco ATLAS module takes care of electrical characterization for the device. These two simulators results were analyzed with Taguchi method to aid in design and optimizing process parameters. Threshold voltage (VTH) results were used as the evaluation parameters. The results show that the VTH value 0.1099 V for NMOS can be achieved respectively, much closer to the ITRS prediction than our previous L9 experiment result. As the conclusion, by utilizing L18 Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.1099 V that is well within ITRS 2003 prediction for 32nm transistor � 2012 American Institute of Physics. Final 2023-12-28T06:30:10Z 2023-12-28T06:30:10Z 2012 Conference paper 10.1063/1.4757531 2-s2.0-84874145255 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84874145255&doi=10.1063%2f1.4757531&partnerID=40&md5=d67ee74b60a32de8c7844f54df510605 https://irepository.uniten.edu.my/handle/123456789/29472 1482 543 549 Scopus
institution	Universiti Tenaga Nasional
building	UNITEN Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Tenaga Nasional
content_source	UNITEN Institutional Repository
url_provider	http://dspace.uniten.edu.my/
topic	Compensation Implantation HALO S/D implantation Silicon MOSFET 32nm Taguchi L18 Taguchi Method Threshold voltage
spellingShingle	Compensation Implantation HALO S/D implantation Silicon MOSFET 32nm Taguchi L18 Taguchi Method Threshold voltage Elgomati H.A. Majlis B.Y. Ahmad I. Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method
description	This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilicon thickness and silicide annealing time. The setting of process parameters were determined by Taguchi method L18 experimental design. From there, the level of importance of each of the process parameters on threshold voltage was determined using analysis of variance (ANOVA). Transistor fabrication was performed by using Silvaco ATHENA module. Silvaco ATLAS module takes care of electrical characterization for the device. These two simulators results were analyzed with Taguchi method to aid in design and optimizing process parameters. Threshold voltage (VTH) results were used as the evaluation parameters. The results show that the VTH value 0.1099 V for NMOS can be achieved respectively, much closer to the ITRS prediction than our previous L9 experiment result. As the conclusion, by utilizing L18 Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.1099 V that is well within ITRS 2003 prediction for 32nm transistor � 2012 American Institute of Physics.
author2	36536722700
author_facet	36536722700 Elgomati H.A. Majlis B.Y. Ahmad I.
format	Conference paper
author	Elgomati H.A. Majlis B.Y. Ahmad I.
author_sort	Elgomati H.A.
title	Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method
title_short	Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method
title_full	Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method
title_fullStr	Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method
title_full_unstemmed	Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method
title_sort	modeling and optimizing of threshold voltage of 32nm nmos transistor using l18 orthogonal array taguchi method
publishDate	2023
_version_	1806424129598914560
score	13.222552

Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method

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