Configurations of memristor-based APUF for improved performance
The memristor-based arbiter PUF (APUF) has great potential to be used for hardware security purposes. Its advantage is in its challenge-dependent delays, which cannot be modeled by machine learning algorithms. In this paper, further improvement is proposed, which are circuit configurations to the me...
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Institute of Advanced Engineering and Science
2023
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my.uniten.dspace-247512023-05-29T15:26:40Z Configurations of memristor-based APUF for improved performance Teo J.H.L. Hashim N.A.N. Ghazali A. Hamid F.A. 57191483647 57191482406 36441299400 6603573875 The memristor-based arbiter PUF (APUF) has great potential to be used for hardware security purposes. Its advantage is in its challenge-dependent delays, which cannot be modeled by machine learning algorithms. In this paper, further improvement is proposed, which are circuit configurations to the memristor-based APUF. Two configuration aspects were introduced namely varying the number of memristor per transistor, and the number of challenge and response bits. The purpose of the configurations is to introduce additional variation to the PUF, thereby improve PUF performance in terms of uniqueness, uniformity, and bit-aliasing; as well as resistance against support vector machine (SVM). Monte Carlo simulations were carried out on 180 nm and 130 nm, where both CMOS technologies have produced uniqueness, uniformity, and bit-aliasing values close to the ideal 50%; as well as SVM prediction accuracies no higher than 52.3%, therefore indicating excellent PUF performance. � 2019 Institute of Advanced Engineering and Science. Final 2023-05-29T07:26:39Z 2023-05-29T07:26:39Z 2019 Article 10.11591/eei.v8i1.1401 2-s2.0-85065259811 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85065259811&doi=10.11591%2feei.v8i1.1401&partnerID=40&md5=4b5a4687c013af569d816ae18da96d9f https://irepository.uniten.edu.my/handle/123456789/24751 8 1 74 82 All Open Access, Bronze, Green Institute of Advanced Engineering and Science Scopus |
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The memristor-based arbiter PUF (APUF) has great potential to be used for hardware security purposes. Its advantage is in its challenge-dependent delays, which cannot be modeled by machine learning algorithms. In this paper, further improvement is proposed, which are circuit configurations to the memristor-based APUF. Two configuration aspects were introduced namely varying the number of memristor per transistor, and the number of challenge and response bits. The purpose of the configurations is to introduce additional variation to the PUF, thereby improve PUF performance in terms of uniqueness, uniformity, and bit-aliasing; as well as resistance against support vector machine (SVM). Monte Carlo simulations were carried out on 180 nm and 130 nm, where both CMOS technologies have produced uniqueness, uniformity, and bit-aliasing values close to the ideal 50%; as well as SVM prediction accuracies no higher than 52.3%, therefore indicating excellent PUF performance. � 2019 Institute of Advanced Engineering and Science. |
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57191483647 |
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57191483647 Teo J.H.L. Hashim N.A.N. Ghazali A. Hamid F.A. |
| format |
Article |
| author |
Teo J.H.L. Hashim N.A.N. Ghazali A. Hamid F.A. |
| spellingShingle |
Teo J.H.L. Hashim N.A.N. Ghazali A. Hamid F.A. Configurations of memristor-based APUF for improved performance |
| author_sort |
Teo J.H.L. |
| title |
Configurations of memristor-based APUF for improved performance |
| title_short |
Configurations of memristor-based APUF for improved performance |
| title_full |
Configurations of memristor-based APUF for improved performance |
| title_fullStr |
Configurations of memristor-based APUF for improved performance |
| title_full_unstemmed |
Configurations of memristor-based APUF for improved performance |
| title_sort |
configurations of memristor-based apuf for improved performance |
| publisher |
Institute of Advanced Engineering and Science |
| publishDate |
2023 |
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1806428007187873792 |
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13.211869 |