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A comparative study of Smart Card design with Memory ciphering system on Arm-Based FPGA

Memory ciphering system is amechanism to secure the data in non-volatile memories of the system using standard encryption module and other security protectiom. Memory ciphering system in a smart card consists of three impodant units. Advanced Encryption Standard (AES) cipher, Random Number Generator...

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Main Authors: Yaakob W.F., Aris H., Sampe J.
Other Authors: 36619864600
Format: Article
Published: Medwell Journals 2023
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spelling my.uniten.dspace-241952023-05-29T14:56:45Z A comparative study of Smart Card design with Memory ciphering system on Arm-Based FPGA Yaakob W.F. Aris H. Sampe J. 36619864600 13608397500 23095535500 Memory ciphering system is amechanism to secure the data in non-volatile memories of the system using standard encryption module and other security protectiom. Memory ciphering system in a smart card consists of three impodant units. Advanced Encryption Standard (AES) cipher, Random Number Generator (RNG) and ScramblerIDescrambler. It is built imide the Memory Management Processing Unit (MMPU) for securlng data transactions with the smart cardmemories Ths study presents the results of a comparative study performed between Xilinx's and Intel's (previously Altera) Advanced RISC Machnes (ARM) based Field Programmable Gate Array (FPGA) in prototyping smart card design with memory ciphering system. The smart card design is implemented in Xilinx's Zynq-7000 XC7020-1-CLG484 and Intel's Cyclone V System-on-a-Chp (SoC) 5 CSEMA 5 F 31 C6N devices. The objective of this study is to identify the optimum FPGA platform for the prototype. The comparative study between the two ARM-based FPGA implementations is explained in terms of logics utilization and time requirements. The memory ciphering system in the smart card is capable to complete in 40 nsec that is a single CPU clock cycle of the smart card. Results obtained showed that the implementation in the Intel Cyclone V SoC has the least utilized logics and the highest maximum frequency whch are 8.313 slices and 195 MHz, respectively. Since, the smart card prototyping in FPGA is the prerequisite for its Application Specific Integrated Circuit (ASIC) implementation, findngs from this study senre as a good reference for enhancing secure smart card performance especially for logic optimization in ASIC. � 2018, Medwell Journals. Final 2023-05-29T06:56:45Z 2023-05-29T06:56:45Z 2018 Article 10.3923/jeasci.2018.2638.2646 2-s2.0-85049509989 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85049509989&doi=10.3923%2fjeasci.2018.2638.2646&partnerID=40&md5=3a1525d53e54c8b7247055b7d770dd45 https://irepository.uniten.edu.my/handle/123456789/24195 13 9 2638 2646 Medwell Journals Scopus
institution Universiti Tenaga Nasional
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country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
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description Memory ciphering system is amechanism to secure the data in non-volatile memories of the system using standard encryption module and other security protectiom. Memory ciphering system in a smart card consists of three impodant units. Advanced Encryption Standard (AES) cipher, Random Number Generator (RNG) and ScramblerIDescrambler. It is built imide the Memory Management Processing Unit (MMPU) for securlng data transactions with the smart cardmemories Ths study presents the results of a comparative study performed between Xilinx's and Intel's (previously Altera) Advanced RISC Machnes (ARM) based Field Programmable Gate Array (FPGA) in prototyping smart card design with memory ciphering system. The smart card design is implemented in Xilinx's Zynq-7000 XC7020-1-CLG484 and Intel's Cyclone V System-on-a-Chp (SoC) 5 CSEMA 5 F 31 C6N devices. The objective of this study is to identify the optimum FPGA platform for the prototype. The comparative study between the two ARM-based FPGA implementations is explained in terms of logics utilization and time requirements. The memory ciphering system in the smart card is capable to complete in 40 nsec that is a single CPU clock cycle of the smart card. Results obtained showed that the implementation in the Intel Cyclone V SoC has the least utilized logics and the highest maximum frequency whch are 8.313 slices and 195 MHz, respectively. Since, the smart card prototyping in FPGA is the prerequisite for its Application Specific Integrated Circuit (ASIC) implementation, findngs from this study senre as a good reference for enhancing secure smart card performance especially for logic optimization in ASIC. � 2018, Medwell Journals.
author2 36619864600
author_facet 36619864600
Yaakob W.F.
Aris H.
Sampe J.
format Article
author Yaakob W.F.
Aris H.
Sampe J.
spellingShingle Yaakob W.F.
Aris H.
Sampe J.
A comparative study of Smart Card design with Memory ciphering system on Arm-Based FPGA
author_sort Yaakob W.F.
title A comparative study of Smart Card design with Memory ciphering system on Arm-Based FPGA
title_short A comparative study of Smart Card design with Memory ciphering system on Arm-Based FPGA
title_full A comparative study of Smart Card design with Memory ciphering system on Arm-Based FPGA
title_fullStr A comparative study of Smart Card design with Memory ciphering system on Arm-Based FPGA
title_full_unstemmed A comparative study of Smart Card design with Memory ciphering system on Arm-Based FPGA
title_sort comparative study of smart card design with memory ciphering system on arm-based fpga
publisher Medwell Journals
publishDate 2023
_version_ 1806428227389882368
score 13.222552

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