Reusable data-path architecture for encryption-then-authentication on FPGA
This paper proposes reusable data-path architecture for lightweight cryptography algorithms, reusing some similar hardware components for both encryption and authentication. In addition to efforts by many researches to optimize hardware architectures, to reduce hardware resources, our proposal is to...
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my.uniten.dspace-229702023-05-29T14:13:49Z Reusable data-path architecture for encryption-then-authentication on FPGA Abbas Y.A. Jidin R. Jamil N. Zaba M.R. 56417806700 6508169028 36682671900 24726154700 This paper proposes reusable data-path architecture for lightweight cryptography algorithms, reusing some similar hardware components for both encryption and authentication. In addition to efforts by many researches to optimize hardware architectures, to reduce hardware resources, our proposal is to reuse identical functional blocks within crypto-algorithms targeting for more secure cryptography like Message Authentication Code (MAC), authenticated encryption such as Encrypt-then-MAC (EtM) on Field Programmable Gate Arrays (FPGA). For this proposed reusable data-path, we have chosen LED algorithm for encryption and then PHOTON to generate the MAC code. Instead of creating two different circuits, one for PHOTON and another for LED, our proposal�s is to reuse some of identical block functions repeatedly, therefore reduce the size of required circuit area. Reuse of resources or identical functions however require controllers that enable sharing of data path that can also has different �rounds� of transforms required for different modes either PHOTON or LED in this case, in addition to controllers for individual algorithm. Also to enable comparable computation speed, the data-path has to be further refined, an improvement needed at least on par or better than the current techniques. For PHOTON data-path, we have improved performance of Mix-Columns, focusing on lengthy clock cycle of Galois polynomial multiplication. The results show that this proposed EtM hardware architecture achieves significant improvements, up to 587 MHz, 1336 Mbps and 3.2 Mbps/slices, for maximum frequency, throughput and efficiency, respectively. � 2016 Praise Worthy Prize S.r.l. - All rights reserved. Final 2023-05-29T06:13:48Z 2023-05-29T06:13:48Z 2016 Article 10.15866/irecos.v11i1.8367 2-s2.0-84964207167 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84964207167&doi=10.15866%2firecos.v11i1.8367&partnerID=40&md5=4c872127eaba275d74778cdda032d5da https://irepository.uniten.edu.my/handle/123456789/22970 11 1 56 63 Praise Worthy Prize Scopus |
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This paper proposes reusable data-path architecture for lightweight cryptography algorithms, reusing some similar hardware components for both encryption and authentication. In addition to efforts by many researches to optimize hardware architectures, to reduce hardware resources, our proposal is to reuse identical functional blocks within crypto-algorithms targeting for more secure cryptography like Message Authentication Code (MAC), authenticated encryption such as Encrypt-then-MAC (EtM) on Field Programmable Gate Arrays (FPGA). For this proposed reusable data-path, we have chosen LED algorithm for encryption and then PHOTON to generate the MAC code. Instead of creating two different circuits, one for PHOTON and another for LED, our proposal�s is to reuse some of identical block functions repeatedly, therefore reduce the size of required circuit area. Reuse of resources or identical functions however require controllers that enable sharing of data path that can also has different �rounds� of transforms required for different modes either PHOTON or LED in this case, in addition to controllers for individual algorithm. Also to enable comparable computation speed, the data-path has to be further refined, an improvement needed at least on par or better than the current techniques. For PHOTON data-path, we have improved performance of Mix-Columns, focusing on lengthy clock cycle of Galois polynomial multiplication. The results show that this proposed EtM hardware architecture achieves significant improvements, up to 587 MHz, 1336 Mbps and 3.2 Mbps/slices, for maximum frequency, throughput and efficiency, respectively. � 2016 Praise Worthy Prize S.r.l. - All rights reserved. |
| author2 |
56417806700 |
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56417806700 Abbas Y.A. Jidin R. Jamil N. Zaba M.R. |
| format |
Article |
| author |
Abbas Y.A. Jidin R. Jamil N. Zaba M.R. |
| spellingShingle |
Abbas Y.A. Jidin R. Jamil N. Zaba M.R. Reusable data-path architecture for encryption-then-authentication on FPGA |
| author_sort |
Abbas Y.A. |
| title |
Reusable data-path architecture for encryption-then-authentication on FPGA |
| title_short |
Reusable data-path architecture for encryption-then-authentication on FPGA |
| title_full |
Reusable data-path architecture for encryption-then-authentication on FPGA |
| title_fullStr |
Reusable data-path architecture for encryption-then-authentication on FPGA |
| title_full_unstemmed |
Reusable data-path architecture for encryption-then-authentication on FPGA |
| title_sort |
reusable data-path architecture for encryption-then-authentication on fpga |
| publisher |
Praise Worthy Prize |
| publishDate |
2023 |
| _version_ |
1806424222097997824 |
| score |
13.222552 |