Staff View: Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method

Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method

In this research paper, the effects of variation on the process parameters were optimised while designing a nano-scaled p-type MOSFET (metal-oxide-semiconductor field-effect transistor) planar device for 22 nm technology. The aim of this procedure is to meet the minimum leakage current (IOFF) by opt...

Full description

Saved in:

Bibliographic Details
Main Authors:	Afifah Maheran A.H., Menon P.S., Ahmad I., Salehuddin F., Mohd Zain A.S.
Other Authors:	36570222300
Format:	Article
Published:	Universiti Teknikal Malaysia Melaka 2023
Tags:	Add Tag No Tags, Be the first to tag this record!

id	my.uniten.dspace-22663
record_format	dspace
spelling	my.uniten.dspace-226632023-05-29T14:11:31Z Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method Afifah Maheran A.H. Menon P.S. Ahmad I. Salehuddin F. Mohd Zain A.S. 36570222300 57201289731 12792216600 36239165300 55925762500 In this research paper, the effects of variation on the process parameters were optimised while designing a nano-scaled p-type MOSFET (metal-oxide-semiconductor field-effect transistor) planar device for 22 nm technology. The aim of this procedure is to meet the minimum leakage current (IOFF) by optimising the process parameters as leakage current. It is one of the characteristics that must be taken into account for device functionality. The gate structure of the device consists of Titanium dioxide (TiO2) that functions as the high permittivity material (high-k) dielectric and Tungsten silicide (WSix) metal gate, where it is deposited on top of the TiO2 high-k layer. The fabrication process was designed using an industrial-based numerical simulator. This simulator was then aided in design with the L9 Taguchi's orthogonal array method to optimise the process parameters to achieve the best combination of the process parameters with the lowest leakage current. The objective is to obtain IOFF values using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The results of the factor effect on the SNR clearly shows that the Halo implantation tilting angle has the greatest influence with 52.47% in minimising the leakage current of the device where the implantation tilting angle is 35�. It is followed by the Halo implantation dose with 34.23% effect, gate oxide growth annealing temperature was ranked third at 12.29% effect and metal gate annealing temperature has the least influence with 1.01%. The final results in characterising and modelling the process parameters of the 22nm PMOS device technology with reference to the prediction by the International Technology Roadmap for Semiconductors (ITRS) succeeded, where the result of the IOFF value was lower than the predicted value which is less than 100 nA/?m. Final 2023-05-29T06:11:31Z 2023-05-29T06:11:31Z 2016 Article 2-s2.0-85011419004 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85011419004&partnerID=40&md5=cf7b95a09cd5b012dd38f0ac8925b1d2 https://irepository.uniten.edu.my/handle/123456789/22663 8 9 19 23 Universiti Teknikal Malaysia Melaka Scopus
institution	Universiti Tenaga Nasional
building	UNITEN Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Tenaga Nasional
content_source	UNITEN Institutional Repository
url_provider	http://dspace.uniten.edu.my/
description	In this research paper, the effects of variation on the process parameters were optimised while designing a nano-scaled p-type MOSFET (metal-oxide-semiconductor field-effect transistor) planar device for 22 nm technology. The aim of this procedure is to meet the minimum leakage current (IOFF) by optimising the process parameters as leakage current. It is one of the characteristics that must be taken into account for device functionality. The gate structure of the device consists of Titanium dioxide (TiO2) that functions as the high permittivity material (high-k) dielectric and Tungsten silicide (WSix) metal gate, where it is deposited on top of the TiO2 high-k layer. The fabrication process was designed using an industrial-based numerical simulator. This simulator was then aided in design with the L9 Taguchi's orthogonal array method to optimise the process parameters to achieve the best combination of the process parameters with the lowest leakage current. The objective is to obtain IOFF values using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The results of the factor effect on the SNR clearly shows that the Halo implantation tilting angle has the greatest influence with 52.47% in minimising the leakage current of the device where the implantation tilting angle is 35�. It is followed by the Halo implantation dose with 34.23% effect, gate oxide growth annealing temperature was ranked third at 12.29% effect and metal gate annealing temperature has the least influence with 1.01%. The final results in characterising and modelling the process parameters of the 22nm PMOS device technology with reference to the prediction by the International Technology Roadmap for Semiconductors (ITRS) succeeded, where the result of the IOFF value was lower than the predicted value which is less than 100 nA/?m.
author2	36570222300
author_facet	36570222300 Afifah Maheran A.H. Menon P.S. Ahmad I. Salehuddin F. Mohd Zain A.S.
format	Article
author	Afifah Maheran A.H. Menon P.S. Ahmad I. Salehuddin F. Mohd Zain A.S.
spellingShingle	Afifah Maheran A.H. Menon P.S. Ahmad I. Salehuddin F. Mohd Zain A.S. Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method
author_sort	Afifah Maheran A.H.
title	Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method
title_short	Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method
title_full	Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method
title_fullStr	Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method
title_full_unstemmed	Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method
title_sort	process parameter optimisation for minimum leakage current in a 22nm p-type mosfet using taguchi method
publisher	Universiti Teknikal Malaysia Melaka
publishDate	2023
_version_	1806425924149706752
score	13.222552

Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method

Similar Items