PRINCE IP-core on Field Programmable Gate Arrays (FPGA)
This study presents a high execution-speed and low-resource hardware IP-Core of PRINCE light weight block cipher on a Field Programmable Gate Arrays (FPGA). The new FPGA IP-core is to speed-up the performance of PRINCE, superseding software implementation that is typically slow and inefficient. The...
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2023
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my.uniten.dspace-225342023-05-29T14:01:44Z PRINCE IP-core on Field Programmable Gate Arrays (FPGA) Abbas Y.A. Jidin R. Jamil N. Z'aba M.R. Rusli M.E. 56417806700 6508169028 36682671900 24726154700 16246214600 This study presents a high execution-speed and low-resource hardware IP-Core of PRINCE light weight block cipher on a Field Programmable Gate Arrays (FPGA). The new FPGA IP-core is to speed-up the performance of PRINCE, superseding software implementation that is typically slow and inefficient. The design of this IP core is based on concurrent concept in encrypting blocks of 64 bits data, in that each block is executed within one clock cycle, resulting in high throughput and low latency. Though this IP core encrypts data at high speed processing, it consumes relatively low power. The hardware design can allow encryption, decryption and key schedule to utilize identical hardware components, in order to reduce further the FPGA resources. This efficient PRINCE hardware architecture has been coded using Very High speed integrated circuit Hardware Description Language (VHDL). Also, a bus interface has been included as part of PRINCE IP core to allow it to communicate with an on-chip microprocessor. The IP core has been successfully synthesized, mapped, simulated and tested on an FPGA evaluation board. The test program that has been written in "C" to evaluate this IP-Core on a Virtex-403 FPGA board yields an encryption throughput of 2.03 Gbps or resource efficiency of 2.126 Mbps/slice. � Maxwell Scientific Organization, 2015. Final 2023-05-29T06:01:44Z 2023-05-29T06:01:44Z 2015 Article 10.19026/rjaset.10.2447 2-s2.0-84939240869 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84939240869&doi=10.19026%2frjaset.10.2447&partnerID=40&md5=e576191c40ead72bcbf215efcc734b1a https://irepository.uniten.edu.my/handle/123456789/22534 10 8 914 922 All Open Access, Gold, Green Maxwell Science Publications Scopus |
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This study presents a high execution-speed and low-resource hardware IP-Core of PRINCE light weight block cipher on a Field Programmable Gate Arrays (FPGA). The new FPGA IP-core is to speed-up the performance of PRINCE, superseding software implementation that is typically slow and inefficient. The design of this IP core is based on concurrent concept in encrypting blocks of 64 bits data, in that each block is executed within one clock cycle, resulting in high throughput and low latency. Though this IP core encrypts data at high speed processing, it consumes relatively low power. The hardware design can allow encryption, decryption and key schedule to utilize identical hardware components, in order to reduce further the FPGA resources. This efficient PRINCE hardware architecture has been coded using Very High speed integrated circuit Hardware Description Language (VHDL). Also, a bus interface has been included as part of PRINCE IP core to allow it to communicate with an on-chip microprocessor. The IP core has been successfully synthesized, mapped, simulated and tested on an FPGA evaluation board. The test program that has been written in "C" to evaluate this IP-Core on a Virtex-403 FPGA board yields an encryption throughput of 2.03 Gbps or resource efficiency of 2.126 Mbps/slice. � Maxwell Scientific Organization, 2015. |
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56417806700 |
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56417806700 Abbas Y.A. Jidin R. Jamil N. Z'aba M.R. Rusli M.E. |
| format |
Article |
| author |
Abbas Y.A. Jidin R. Jamil N. Z'aba M.R. Rusli M.E. |
| spellingShingle |
Abbas Y.A. Jidin R. Jamil N. Z'aba M.R. Rusli M.E. PRINCE IP-core on Field Programmable Gate Arrays (FPGA) |
| author_sort |
Abbas Y.A. |
| title |
PRINCE IP-core on Field Programmable Gate Arrays (FPGA) |
| title_short |
PRINCE IP-core on Field Programmable Gate Arrays (FPGA) |
| title_full |
PRINCE IP-core on Field Programmable Gate Arrays (FPGA) |
| title_fullStr |
PRINCE IP-core on Field Programmable Gate Arrays (FPGA) |
| title_full_unstemmed |
PRINCE IP-core on Field Programmable Gate Arrays (FPGA) |
| title_sort |
prince ip-core on field programmable gate arrays (fpga) |
| publisher |
Maxwell Science Publications |
| publishDate |
2023 |
| _version_ |
1806426380324306944 |
| score |
13.222552 |