TOPOLOGICAL DESIGN EXPLORATION FOR 10×10 MESH WIRELESS NETWORK-ON-CHIP
Wireless Network on Chip is an innovative technique to resolving latency and power consumption limitations in Network-on-Chip (NoC). This project targets to improve the performance of the Wireless Network on Chip (WiNoC) on different radio hub location for 10×10 MESH topology. As WiNoC has gotten...
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| Main Author: | |
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| Format: | Final Year Project Report |
| Language: | English English |
| Published: |
Universiti Malaysia Sarawak
2022
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| Subjects: | |
| Online Access: | http://ir.unimas.my/id/eprint/39467/1/Raynold%20Gerijih%20Belasap%20Anak%20David%20-%20%2024pages.pdf http://ir.unimas.my/id/eprint/39467/4/Raynold%20Gerijih%20Belasap.pdf http://ir.unimas.my/id/eprint/39467/ |
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| Summary: | Wireless Network on Chip is an innovative technique to resolving latency and power
consumption limitations in Network-on-Chip (NoC). This project targets to improve the
performance of the Wireless Network on Chip (WiNoC) on different radio hub location
for 10×10 MESH topology. As WiNoC has gotten bigger as a communication technology,
it has encountered issues with topological performance that must be addressed. The
system with high latency will affect the network throughput. Thus, the power
consumption by system might get higher due to many workloads. The power consumption
model and the system interference model have been offered as methods for achieving the
desired topology generation. By utilizing the cycle accurate on chip simulator (Noxim),
the experimental simulation compares three topologies with different placements for the
radio hub in order to assess how well each one performs in terms of latency, network
throughput, and energy consumption. By this experiment, the best topology is the 4-hub
topology (WiNoC). |
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