Design and Implementation of MDS Hash Function Algorithm Using Verilog HDL
Over the past 20 years, the demand of computers and the Internet has been increasing and people have paid a growing attention to information and network security. In result, various encryption algorithms coming into being. Cryptographic algorithm has become one of the most essential features of e...
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| Main Authors: | , , , |
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| 格式: | Article |
| 語言: | English |
| 出版: |
Springer
2020
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| 主題: | |
| 在線閱讀: | http://ir.unimas.my/id/eprint/36269/1/Shamsiah%20Suhaili.pdf http://ir.unimas.my/id/eprint/36269/ https://www.springer.com/gp/book/9789811624056 |
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| 總結: | Over the past 20 years, the demand of computers and the Internet has been
increasing and people have paid a growing attention to information and network security.
In result, various encryption algorithms coming into being. Cryptographic algorithm
has become one of the most essential features of embedded system design. Hash
functions are one of the cryptographies that can be used in both security design applications
and protocol suites. A few distinct applications of hash algorithms are digital
signatures, digital time stamping and the message integrity verification. Among hash
algorithms, MD5 is the most used hash function algorithm. This paper proposed
iterative looping architecture. The architecture includes MD5 padding block, data
path, and a controller. A general concept and implementation of the MD5 hash
function is described. The MD5 hash function modelling was done using Verilog,
compiled with a few targeted virtual Altera Quartus devices, and simulated using
ModelSim. Its performance in terms of frequency and throughput is compared with
other MD5 implementations. The maximum frequency achieved is 111.45 MHz, and
the throughput of iterative looping design was increased significantly to 864.58 Mbps
using family device of Arria II GX. The improved performance of the implementation
is the main goal of the design presented herein. |
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