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Taguchi Method for p-MOS threshold voltage optimization with a gate length of 22nm

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Main Authors: A. H. Afifah Maheran, Izwanizam, Yahaya, F. Salehuddin, K. E. Kaharudin
Other Authors: afifah@utem.edu.my
Format: Article
Language:English
Published: Universiti Malaysia Perlis (UniMAP) 2023
Subjects:
Taguchi
p-type
Statistical
Optimization
Graphene
P-type
Online Access:http://dspace.unimap.edu.my:80/xmlui/handle/123456789/78125
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spelling my.unimap-781252023-03-10T07:08:46Z Taguchi Method for p-MOS threshold voltage optimization with a gate length of 22nm A. H. Afifah Maheran Izwanizam, Yahaya F. Salehuddin K. E. Kaharudin A. H. Afifah Maheran afifah@utem.edu.my Micro & Nano Electronics Research Group (MiNE), Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka (UTeM) Taguchi p-type Statistical Optimization Graphene P-type Link to publisher's homepage at http://ijneam.unimap.edu.my/ This paper describes the virtual design of a 22nm gate length p-type metal oxide semiconductor, PMOS. Silvaco, TCAD tools were used to fabricate the device design and to characterize the device’s electrical properties. Fixed field scaling rules are applied to obtain the transistor’s electrical parameters set by ITRS 2013. In order to take the challenges that arise in the fabrication of nano-sized transistors and enhance their performance, advanced and novel technologies are applied. Using the statistical modelling of L9 Taguchi methodology, the development process is primarily focused on the tool's edge voltage. Four parameters have been divided into three distinct steps in order to conduct nine different experiments. The final confirmation result indicates that VTH is closer to the nominal value -0.206V following optimization techniques. This matches the ITRS 2013 requirements for high performance. This paper examines the design of a p-MOS double gate containing a layer of graphene as it is known to have a high mobility value 2023-03-10T07:08:46Z 2023-03-10T07:08:46Z 2023-01 Article International Journal of Nanoelectronics and Materials, vol.16(1), 2023, pages 1-9 1985-5761 (Printed) 1997-4434 (Online) http://dspace.unimap.edu.my:80/xmlui/handle/123456789/78125 http://ijneam.unimap.edu.my en Universiti Malaysia Perlis (UniMAP)
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Taguchi
p-type
Statistical
Optimization
Graphene
P-type
spellingShingle Taguchi
p-type
Statistical
Optimization
Graphene
P-type
A. H. Afifah Maheran
Izwanizam, Yahaya
F. Salehuddin
K. E. Kaharudin
A. H. Afifah Maheran
Taguchi Method for p-MOS threshold voltage optimization with a gate length of 22nm
description Link to publisher's homepage at http://ijneam.unimap.edu.my/
author2 afifah@utem.edu.my
author_facet afifah@utem.edu.my
A. H. Afifah Maheran
Izwanizam, Yahaya
F. Salehuddin
K. E. Kaharudin
A. H. Afifah Maheran
format Article
author A. H. Afifah Maheran
Izwanizam, Yahaya
F. Salehuddin
K. E. Kaharudin
A. H. Afifah Maheran
author_sort A. H. Afifah Maheran
title Taguchi Method for p-MOS threshold voltage optimization with a gate length of 22nm
title_short Taguchi Method for p-MOS threshold voltage optimization with a gate length of 22nm
title_full Taguchi Method for p-MOS threshold voltage optimization with a gate length of 22nm
title_fullStr Taguchi Method for p-MOS threshold voltage optimization with a gate length of 22nm
title_full_unstemmed Taguchi Method for p-MOS threshold voltage optimization with a gate length of 22nm
title_sort taguchi method for p-mos threshold voltage optimization with a gate length of 22nm
publisher Universiti Malaysia Perlis (UniMAP)
publishDate 2023
url http://dspace.unimap.edu.my:80/xmlui/handle/123456789/78125
_version_ 1772813134404255744
score 13.226497

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