Staff View: Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication

Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication

Master of Science (Microelectronic Engineering)

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Bibliographic Details
Main Author:	Amiza, Rasmi
Other Authors:	Uda Hashim, Assoc. Prof. Dr.
Format:	Thesis
Language:	English
Published:	Kolej Universiti Kejuruteraan Utara Malaysia (KUKUM) 2019
Subjects:	Sol Single-Electron Transistor (SET) Single-electron transistor (SET) Solid state electronic Silicon-on-insulator technology Single-Electron technology Semiconductor devices
Online Access:	http://dspace.unimap.edu.my:80/xmlui/handle/123456789/63459
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id	my.unimap-63459
record_format	dspace
spelling	my.unimap-634592019-11-29T07:34:53Z Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication Amiza, Rasmi Uda Hashim, Assoc. Prof. Dr. Sol Single-Electron Transistor (SET) Single-electron transistor (SET) Solid state electronic Silicon-on-insulator technology Single-Electron technology Semiconductor devices Master of Science (Microelectronic Engineering) Single-electron transistor (SET) is one of the promising nanotechnologies and distinguished by a very small device size and low power dissipation. This project explains the SET mask design, SET process flow development, and SET process and device simulation. The SET mask design consists of four level masks namely source and drain mask, polysilicon gate mask, contact mask, and metal mask. These masks were designed in nanometer (10-9 m) size using ELPHY Quantum GDS II Editor Software. The source and drain mask is connected by a nanowire placed between source and drain regions. The nanowire is designed with dimension of approximately 100 nm long and 10 nm wide. The process flow which includes the detailed parameters is developed for SET process and device simulation. This process flow consists of ten process modules include wafer cleaning process, material deposition, source/drain and nanowire formation , thermal oxidation, polysilicon deposition, polysilicon gate formation, source/drain implantation, contact formation, metal deposition and formation, and finally annealing and alloying process. The Synopsys TCAD simulation tools are utilized in SET process and device simulation work. The process and device simulation result shows that the single-electron transistor design with a 100 nm length and 10 nm width of the nanowire is working at room temperature (300 K) operation with a capacitance 0.4297 x 10-18F and a charging energy 186.4 meV. 2019-11-29T07:34:53Z 2019-11-29T07:34:53Z 2006-04 Thesis http://dspace.unimap.edu.my:80/xmlui/handle/123456789/63459 en Kolej Universiti Kejuruteraan Utara Malaysia (KUKUM) School of Microelectronic Engineering
institution	Universiti Malaysia Perlis
building	UniMAP Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Malaysia Perlis
content_source	UniMAP Library Digital Repository
url_provider	http://dspace.unimap.edu.my/
language	English
topic	Sol Single-Electron Transistor (SET) Single-electron transistor (SET) Solid state electronic Silicon-on-insulator technology Single-Electron technology Semiconductor devices
spellingShingle	Sol Single-Electron Transistor (SET) Single-electron transistor (SET) Solid state electronic Silicon-on-insulator technology Single-Electron technology Semiconductor devices Amiza, Rasmi Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication
description	Master of Science (Microelectronic Engineering)
author2	Uda Hashim, Assoc. Prof. Dr.
author_facet	Uda Hashim, Assoc. Prof. Dr. Amiza, Rasmi
format	Thesis
author	Amiza, Rasmi
author_sort	Amiza, Rasmi
title	Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication
title_short	Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication
title_full	Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication
title_fullStr	Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication
title_full_unstemmed	Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication
title_sort	design, simulation and process development for sol single-electron transistor (set) fabrication
publisher	Kolej Universiti Kejuruteraan Utara Malaysia (KUKUM)
publishDate	2019
url	http://dspace.unimap.edu.my:80/xmlui/handle/123456789/63459
_version_	1651868842329112576
score	13.222552

Design, simulation and process development for Sol Single-Electron Transistor (SET) fabrication

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