Comparison of delays between 4-bits ripple-carry adder and 4-bits carry look-ahead adder using logical effort method

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Main Author: Siti Nurhanani, Che Yahaya
Other Authors: Norina Idris
Format: Learning Object
Language:English
Published: Universiti Malaysia Perlis (UniMAP) 2015
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Online Access:http://dspace.unimap.edu.my:80/xmlui/handle/123456789/40277
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spelling my.unimap-402772015-07-14T03:27:06Z Comparison of delays between 4-bits ripple-carry adder and 4-bits carry look-ahead adder using logical effort method Siti Nurhanani, Che Yahaya Norina Idris Ripple-Carry Adder Circuit (RCA) Circuit topologies Carry look-ahead adder (CLA) Access is limited to UniMAP community. In this project, two types of circuit topologies has been designed which are the 4-B its Ripple-Carry Adder Circuit (RCA) and the 4-Bits Carry Look-Ahead Adder Circuit (CLA). Delays in RCA circuit will be compared between before and after applying the Logical Effort method to determine which circuit is good in terms of having a faster response between input and output. Besides, RCA circuit also will be compared with CLA circuit to show that different circuit topologies with the same circuit function would have different circuit delays. The Logical Effort method, includessome steps such as path effort computation, best number of stages computation, minimum delay estimation, best stage effort determination and sizing the gates in the RCA circuit. In this project, after applying the Logical Effort method, the circuit will have less delays compared to the same circuit that does not apply Logical Effort, with an improvement is about 44.15%. Meanwhile, the average improvement of CLA over RCA is about 64.85% , which means different circuit topologies would have different delays. The more complex a circuit is (high fan-in) it produces more delays. Gates number did not affected the delays in a circuit which sometimes, by having addition stages with same circuit function would improved the delays and produced fast response circuit. 2015-07-14T03:27:06Z 2015-07-14T03:27:06Z 2011-06 Learning Object http://dspace.unimap.edu.my:80/xmlui/handle/123456789/40277 en Universiti Malaysia Perlis (UniMAP) School of Microelectronic Engineering
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Ripple-Carry Adder Circuit (RCA)
Circuit topologies
Carry look-ahead adder (CLA)
spellingShingle Ripple-Carry Adder Circuit (RCA)
Circuit topologies
Carry look-ahead adder (CLA)
Siti Nurhanani, Che Yahaya
Comparison of delays between 4-bits ripple-carry adder and 4-bits carry look-ahead adder using logical effort method
description Access is limited to UniMAP community.
author2 Norina Idris
author_facet Norina Idris
Siti Nurhanani, Che Yahaya
format Learning Object
author Siti Nurhanani, Che Yahaya
author_sort Siti Nurhanani, Che Yahaya
title Comparison of delays between 4-bits ripple-carry adder and 4-bits carry look-ahead adder using logical effort method
title_short Comparison of delays between 4-bits ripple-carry adder and 4-bits carry look-ahead adder using logical effort method
title_full Comparison of delays between 4-bits ripple-carry adder and 4-bits carry look-ahead adder using logical effort method
title_fullStr Comparison of delays between 4-bits ripple-carry adder and 4-bits carry look-ahead adder using logical effort method
title_full_unstemmed Comparison of delays between 4-bits ripple-carry adder and 4-bits carry look-ahead adder using logical effort method
title_sort comparison of delays between 4-bits ripple-carry adder and 4-bits carry look-ahead adder using logical effort method
publisher Universiti Malaysia Perlis (UniMAP)
publishDate 2015
url http://dspace.unimap.edu.my:80/xmlui/handle/123456789/40277
_version_ 1643799317646934016
score 13.222552