Cover Image

A study of proper integrated circuit (IC) layout techniques for a parallel adder

Access is limited to UniMAP community.

Saved in:
Bibliographic Details
Main Author: Kau, Zee Shuang
Other Authors: Norina Idris
Format: Learning Object
Language:English
Published: Universiti Malaysia Perlis (UniMAP) 2015
Subjects:
Integrated Circuit (IC)
Parallel adder
CMOS technology
Parallel adder > Design and construction
Online Access:http://dspace.unimap.edu.my:80/xmlui/handle/123456789/40274
Tags: Add Tag
No Tags, Be the first to tag this record!
id my.unimap-40274
record_format dspace
spelling my.unimap-402742015-07-14T03:14:44Z A study of proper integrated circuit (IC) layout techniques for a parallel adder Kau, Zee Shuang Norina Idris Integrated Circuit (IC) Parallel adder CMOS technology Parallel adder -- Design and construction Access is limited to UniMAP community. This report presents the proper Integrated Circuit (IC) layout techniques for a parallel adder. The layout produced for this parallel adder is presented in this report. In order to design and to get a good layout, understanding on proper layout design rules and techniques are needed. The layout is designed using rules from TSMC 0.35μm CMOS technology. When designing a layout of parallel adder, layout rules such as minimum features, minimum spacing, surround, exact size, well rules, transistors rules and contact rules and specific techniques such as floorplanning, placement and routing must be followed. Parallel adder is designed by referring to the full adder. Four individual full adder cells are connected to give parallel inputs and ripple carry. The schematic and layout of the parallel adder are designed in Mentor Graphics DA and IC station. The layout has been completed design using POLY, Metal1 and Metal2 for connections. After the layout of parallel adder is finished drawn, the next steps are DRC and LVS simulation. DRC and LVS simulation are used to identify the errors which have all been faced by designer. The project with the title of A Study of Proper Integrated Circuit (IC) Layout Techniques for a Parallel Adder had been successfully. 2015-07-14T03:14:44Z 2015-07-14T03:14:44Z 2011-06 Learning Object http://dspace.unimap.edu.my:80/xmlui/handle/123456789/40274 en Universiti Malaysia Perlis (UniMAP) School of Microelectronic Engineering
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Integrated Circuit (IC)
Parallel adder
CMOS technology
Parallel adder -- Design and construction
spellingShingle Integrated Circuit (IC)
Parallel adder
CMOS technology
Parallel adder -- Design and construction
Kau, Zee Shuang
A study of proper integrated circuit (IC) layout techniques for a parallel adder
description Access is limited to UniMAP community.
author2 Norina Idris
author_facet Norina Idris
Kau, Zee Shuang
format Learning Object
author Kau, Zee Shuang
author_sort Kau, Zee Shuang
title A study of proper integrated circuit (IC) layout techniques for a parallel adder
title_short A study of proper integrated circuit (IC) layout techniques for a parallel adder
title_full A study of proper integrated circuit (IC) layout techniques for a parallel adder
title_fullStr A study of proper integrated circuit (IC) layout techniques for a parallel adder
title_full_unstemmed A study of proper integrated circuit (IC) layout techniques for a parallel adder
title_sort study of proper integrated circuit (ic) layout techniques for a parallel adder
publisher Universiti Malaysia Perlis (UniMAP)
publishDate 2015
url http://dspace.unimap.edu.my:80/xmlui/handle/123456789/40274
_version_ 1643799317348089856
score 13.222552

Similar Items