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Design and fabrication of quantum dot single electron transistors using scanning electron microscopy-based electron-beam nanolithogrphy

Quantum dot single-electron transistor (QD SET) is a nanoscale device operated at very low temperature. To fabricate QD SET operated at room temperature, QD must be fabricated in diameter of 10 nm. QD SET promises very small integrated circuits with ultralow-power consumption. In this research, a QD...

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Main Author: Sutikno
Other Authors: Prof. Dr. Uda Hashim
Format: Thesis
Language:English
Published: Universiti Malaysia Perlis 2012
Subjects:
Quantum dot single-electron transistor (QD SET)
Transistor
Nano devices
ma-N 2403
PMMA 495 K
Online Access:http://dspace.unimap.edu.my/xmlui/handle/123456789/22189
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spelling my.unimap-221892012-12-09T10:33:38Z Design and fabrication of quantum dot single electron transistors using scanning electron microscopy-based electron-beam nanolithogrphy Sutikno Prof. Dr. Uda Hashim Quantum dot single-electron transistor (QD SET) Transistor Nano devices ma-N 2403 PMMA 495 K Quantum dot single-electron transistor (QD SET) is a nanoscale device operated at very low temperature. To fabricate QD SET operated at room temperature, QD must be fabricated in diameter of 10 nm. QD SET promises very small integrated circuits with ultralow-power consumption. In this research, a QD SET was designed using ELPHY Quantum GDSII Editor and fabricated using top down method. The QD SET masks design consists of SET mask for source-drain formation, SET mask for point contact and SET mask for metal pad. In addition, side gate and QD were designed in the same layer as source-drain. QD SET was designed using GDSII Editor with the following dimension: source-drain (3 μm x 3 μm), QD (10-30 nm in diameter), tunnel barriers (8.365 nm in width), side gate (3 μm x 3 μm) and metal pad (20 μm x 10 μm). Silicon on insulator (SOI) was used as the starting material and e- beam lithography system was used to transfer masks patterns. Negative resist ma-N 2403 was used to fabricate source-drain, QD, side gate and metal pad. Whereas positive resist 495K PMMA was used to fabricate point contact. To fabricate QD, silicon was etched using inductively coupled plasma (ICP) etcher and its parameters were optimized. The optimum etch time is 75 s and the optimum oxygen flow rate is 28 sccm. The smallest possible QD etched using ICP etcher in this research is 63 nm. To shrink QD dimension, silicon QD was oxidized through pattern dependent oxidation (PADOX) process using rapid thermal processing (RTP) and furnace. In this research, oxidation time using RTP was optimized in the range of 5-30 s at 1000 °C. Etched silicon samples were oxidized using furnace at 1000 °C in the oxidation time range of 5-30 min. The oxygen flow rate and the nitrogen flow rate were both set at 1 l/min. SiO2-embedded-silicon was characterized using transmission electron microscopy (TEM). The dimensions of QDs in the range of 10-30 nm were achieved and the oxidation rate was optimized as well. The nano multi layers alignment was done using SEM-based e-beam lithography and platinum was used as nano mark. 2012-12-09T10:33:38Z 2012-12-09T10:33:38Z 2009 Thesis http://hdl.handle.net/123456789/22189 en Universiti Malaysia Perlis School of Microelectronic Engineering
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Quantum dot single-electron transistor (QD SET)
Transistor
Nano devices
ma-N 2403
PMMA 495 K
spellingShingle Quantum dot single-electron transistor (QD SET)
Transistor
Nano devices
ma-N 2403
PMMA 495 K
Sutikno
Design and fabrication of quantum dot single electron transistors using scanning electron microscopy-based electron-beam nanolithogrphy
description Quantum dot single-electron transistor (QD SET) is a nanoscale device operated at very low temperature. To fabricate QD SET operated at room temperature, QD must be fabricated in diameter of 10 nm. QD SET promises very small integrated circuits with ultralow-power consumption. In this research, a QD SET was designed using ELPHY Quantum GDSII Editor and fabricated using top down method. The QD SET masks design consists of SET mask for source-drain formation, SET mask for point contact and SET mask for metal pad. In addition, side gate and QD were designed in the same layer as source-drain. QD SET was designed using GDSII Editor with the following dimension: source-drain (3 μm x 3 μm), QD (10-30 nm in diameter), tunnel barriers (8.365 nm in width), side gate (3 μm x 3 μm) and metal pad (20 μm x 10 μm). Silicon on insulator (SOI) was used as the starting material and e- beam lithography system was used to transfer masks patterns. Negative resist ma-N 2403 was used to fabricate source-drain, QD, side gate and metal pad. Whereas positive resist 495K PMMA was used to fabricate point contact. To fabricate QD, silicon was etched using inductively coupled plasma (ICP) etcher and its parameters were optimized. The optimum etch time is 75 s and the optimum oxygen flow rate is 28 sccm. The smallest possible QD etched using ICP etcher in this research is 63 nm. To shrink QD dimension, silicon QD was oxidized through pattern dependent oxidation (PADOX) process using rapid thermal processing (RTP) and furnace. In this research, oxidation time using RTP was optimized in the range of 5-30 s at 1000 °C. Etched silicon samples were oxidized using furnace at 1000 °C in the oxidation time range of 5-30 min. The oxygen flow rate and the nitrogen flow rate were both set at 1 l/min. SiO2-embedded-silicon was characterized using transmission electron microscopy (TEM). The dimensions of QDs in the range of 10-30 nm were achieved and the oxidation rate was optimized as well. The nano multi layers alignment was done using SEM-based e-beam lithography and platinum was used as nano mark.
author2 Prof. Dr. Uda Hashim
author_facet Prof. Dr. Uda Hashim
Sutikno
format Thesis
author Sutikno
author_sort Sutikno
title Design and fabrication of quantum dot single electron transistors using scanning electron microscopy-based electron-beam nanolithogrphy
title_short Design and fabrication of quantum dot single electron transistors using scanning electron microscopy-based electron-beam nanolithogrphy
title_full Design and fabrication of quantum dot single electron transistors using scanning electron microscopy-based electron-beam nanolithogrphy
title_fullStr Design and fabrication of quantum dot single electron transistors using scanning electron microscopy-based electron-beam nanolithogrphy
title_full_unstemmed Design and fabrication of quantum dot single electron transistors using scanning electron microscopy-based electron-beam nanolithogrphy
title_sort design and fabrication of quantum dot single electron transistors using scanning electron microscopy-based electron-beam nanolithogrphy
publisher Universiti Malaysia Perlis
publishDate 2012
url http://dspace.unimap.edu.my/xmlui/handle/123456789/22189
_version_ 1643789589640380416
score 13.222552

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