Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator

Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. A ring oscillator has been widely used as a digital temperature sensor to sense this thermal effect on FPGA...

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Main Authors: Jaafar, Anuar, Soin, Norhayati, Hatta, Sharifah Fatmadiana Wan Muhamad, Irwan Md, Salim Sani
Format: Article
Published: Institution of Engineering and Technology 2019
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Online Access:http://eprints.um.edu.my/24105/
https://doi.org/10.1049/iet-cdt.2019.0072
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spelling my.um.eprints.241052020-03-26T05:07:37Z http://eprints.um.edu.my/24105/ Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator Jaafar, Anuar Soin, Norhayati Hatta, Sharifah Fatmadiana Wan Muhamad Irwan Md, Salim Sani TK Electrical engineering. Electronics Nuclear engineering Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. A ring oscillator has been widely used as a digital temperature sensor to sense this thermal effect on FPGAs. The delay generated by the ring oscillator will vary depending on the temperature environment due to negative bias temperature instability, hot carrier injection and electromigration. It is therefore critical to adopt an accurate ring oscillator design to effectively measure the delay in FGPAs. In this study, a digital temperature sensor with a stable ring oscillator is proposed. Measurement periods of 512 and 4096 clock cycles have been implemented and the relationship between temperature, delay and total count has been established. The results show that as the temperature increases to 100°C, the delay decreases by 3.99 and 33.98% for 512 and 4096 clock cycles, respectively. It has been found that in order to reduce the degradation effect on the Virtex-6 FPGA, adopting a measurement period of 512 clock cycles is the best method. The measured data is successfully validated through a set of simulations. Thus, it may benefit a system designer and industrial player, especially in designing temperature-based FPGAs. © The Institution of Engineering and Technology 2019 Institution of Engineering and Technology 2019 Article PeerReviewed Jaafar, Anuar and Soin, Norhayati and Hatta, Sharifah Fatmadiana Wan Muhamad and Irwan Md, Salim Sani (2019) Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator. IET Computers & Digital Techniques, 13 (5). pp. 405-413. ISSN 1751-8601 https://doi.org/10.1049/iet-cdt.2019.0072 doi:10.1049/iet-cdt.2019.0072
institution Universiti Malaya
building UM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaya
content_source UM Research Repository
url_provider http://eprints.um.edu.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Jaafar, Anuar
Soin, Norhayati
Hatta, Sharifah Fatmadiana Wan Muhamad
Irwan Md, Salim Sani
Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator
description Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. A ring oscillator has been widely used as a digital temperature sensor to sense this thermal effect on FPGAs. The delay generated by the ring oscillator will vary depending on the temperature environment due to negative bias temperature instability, hot carrier injection and electromigration. It is therefore critical to adopt an accurate ring oscillator design to effectively measure the delay in FGPAs. In this study, a digital temperature sensor with a stable ring oscillator is proposed. Measurement periods of 512 and 4096 clock cycles have been implemented and the relationship between temperature, delay and total count has been established. The results show that as the temperature increases to 100°C, the delay decreases by 3.99 and 33.98% for 512 and 4096 clock cycles, respectively. It has been found that in order to reduce the degradation effect on the Virtex-6 FPGA, adopting a measurement period of 512 clock cycles is the best method. The measured data is successfully validated through a set of simulations. Thus, it may benefit a system designer and industrial player, especially in designing temperature-based FPGAs. © The Institution of Engineering and Technology 2019
format Article
author Jaafar, Anuar
Soin, Norhayati
Hatta, Sharifah Fatmadiana Wan Muhamad
Irwan Md, Salim Sani
author_facet Jaafar, Anuar
Soin, Norhayati
Hatta, Sharifah Fatmadiana Wan Muhamad
Irwan Md, Salim Sani
author_sort Jaafar, Anuar
title Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator
title_short Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator
title_full Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator
title_fullStr Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator
title_full_unstemmed Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator
title_sort delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator
publisher Institution of Engineering and Technology
publishDate 2019
url http://eprints.um.edu.my/24105/
https://doi.org/10.1049/iet-cdt.2019.0072
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score 13.211869