Linearity improvement of differential CMOS low noise amplifier
This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using d...
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my.um.eprints.239562020-03-04T02:52:40Z http://eprints.um.edu.my/23956/ Linearity improvement of differential CMOS low noise amplifier Muhamad, Maizan Soin, Norhayati Ramiah, Harikrishnan TK Electrical engineering. Electronics Nuclear engineering This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S21 gain of 18.56 dB, noise figure (NF) of 1.85 dB, S11 of −27.63 dB, S22 of-34.33 dB, S12 of −37.09 dB and IIP3 of-7.79 dBm. © 2019, Institute of Advanced Engineering and Science. All rights reserved. Institute of Advanced Engineering and Science 2019 Article PeerReviewed Muhamad, Maizan and Soin, Norhayati and Ramiah, Harikrishnan (2019) Linearity improvement of differential CMOS low noise amplifier. Indonesian Journal of Electrical Engineering and Computer Science, 14 (1). pp. 407-412. ISSN 2502-4752 http://ijeecs.iaescore.com/index.php/IJEECS/article/view/17164 doi:10.11591/ijeecs.v14.i1.pp407-412 |
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TK Electrical engineering. Electronics Nuclear engineering Muhamad, Maizan Soin, Norhayati Ramiah, Harikrishnan Linearity improvement of differential CMOS low noise amplifier |
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This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S21 gain of 18.56 dB, noise figure (NF) of 1.85 dB, S11 of −27.63 dB, S22 of-34.33 dB, S12 of −37.09 dB and IIP3 of-7.79 dBm. © 2019, Institute of Advanced Engineering and Science. All rights reserved. |
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Article |
author |
Muhamad, Maizan Soin, Norhayati Ramiah, Harikrishnan |
author_facet |
Muhamad, Maizan Soin, Norhayati Ramiah, Harikrishnan |
author_sort |
Muhamad, Maizan |
title |
Linearity improvement of differential CMOS low noise amplifier |
title_short |
Linearity improvement of differential CMOS low noise amplifier |
title_full |
Linearity improvement of differential CMOS low noise amplifier |
title_fullStr |
Linearity improvement of differential CMOS low noise amplifier |
title_full_unstemmed |
Linearity improvement of differential CMOS low noise amplifier |
title_sort |
linearity improvement of differential cmos low noise amplifier |
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Institute of Advanced Engineering and Science |
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2019 |
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http://eprints.um.edu.my/23956/ http://ijeecs.iaescore.com/index.php/IJEECS/article/view/17164 |
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