8-bit Successive Approximation Register Analog-to-Digital (SAR ADC) logic design / Zuhaila Abdul Halim
This thesis presents the design of a 8-bit Successive Approximation Register (S AR) logic of SAR ADC in a HP 0.5um SCN3M Complementary Metal Oxide Semiconductor (CMOS). The architecture of SAR logic consists of 3 modules which are shift register, register low-to-high and code register. From this arc...
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| Format: | Thesis |
| Language: | English |
| Published: |
2006
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| Online Access: | https://ir.uitm.edu.my/id/eprint/98646/1/98646.pdf https://ir.uitm.edu.my/id/eprint/98646/ |
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