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Modeling of “strain technology” on 140nm CMOS devices / Ahmad Sabirin Zoolfakar, Noor Irmahani Mohmad Tahiruddin and Lyly Nyl Ismail

A 140nm Complementary Metal Oxide Semiconductor (CMOS) was designed and simulated to investigate stress effects on device performance. Stress can be divided into two categories which are compressive and tensile stress. Strain technology is capable to introduce stress to the CMOS devices. The strain...

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Main Authors: Zoolfakar, Ahmad Sabirin, Mohmad Tahiruddin, Noor Irmahani, Ismail, Lyly Nyl
Format: Article
Language:English
Published: UiTM Press 2009
Subjects:
Electric apparatus and materials. Electric circuits. Electric networks
Online Access:https://ir.uitm.edu.my/id/eprint/61856/1/61856.pdf
https://ir.uitm.edu.my/id/eprint/61856/
https://jeesr.uitm.edu.my/v1/
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spelling my.uitm.ir.618562022-06-16T07:21:08Z https://ir.uitm.edu.my/id/eprint/61856/ Modeling of “strain technology” on 140nm CMOS devices / Ahmad Sabirin Zoolfakar, Noor Irmahani Mohmad Tahiruddin and Lyly Nyl Ismail Zoolfakar, Ahmad Sabirin Mohmad Tahiruddin, Noor Irmahani Ismail, Lyly Nyl Electric apparatus and materials. Electric circuits. Electric networks A 140nm Complementary Metal Oxide Semiconductor (CMOS) was designed and simulated to investigate stress effects on device performance. Stress can be divided into two categories which are compressive and tensile stress. Strain technology is capable to introduce stress to the CMOS devices. The strain technology can be developed by Silicon Nitride (Si3N4) capping layer, Silicide and Shallow Trench Isolation (STI). The paper discussed on the effect of strain technology on 140nm CMOS device performance focusing on threshold voltage and drain current parameters. ATHENA and ATLAS simulators were used to simulate the fabrication process and to characterize the electrical properties respectively. It can be concluded that STI is better compared to LOCOS for length gate below than 250nm devices. Compressive STI stress enhances by 13.8% PMOS performance while tensile Si3N4 capping layer improve by 1% NMOS performance. In addition CMOS with silicide module improve by 2.5% PMOS drain current. UiTM Press 2009-06 Article PeerReviewed text en https://ir.uitm.edu.my/id/eprint/61856/1/61856.pdf Modeling of “strain technology” on 140nm CMOS devices / Ahmad Sabirin Zoolfakar, Noor Irmahani Mohmad Tahiruddin and Lyly Nyl Ismail. (2009) Journal of Electrical and Electronic Systems Research (JEESR), 2: 1. pp. 1-6. ISSN 1985-5389 https://jeesr.uitm.edu.my/v1/
institution Universiti Teknologi Mara
building Tun Abdul Razak Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Mara
content_source UiTM Institutional Repository
url_provider http://ir.uitm.edu.my/
language English
topic Electric apparatus and materials. Electric circuits. Electric networks
spellingShingle Electric apparatus and materials. Electric circuits. Electric networks
Zoolfakar, Ahmad Sabirin
Mohmad Tahiruddin, Noor Irmahani
Ismail, Lyly Nyl
Modeling of “strain technology” on 140nm CMOS devices / Ahmad Sabirin Zoolfakar, Noor Irmahani Mohmad Tahiruddin and Lyly Nyl Ismail
description A 140nm Complementary Metal Oxide Semiconductor (CMOS) was designed and simulated to investigate stress effects on device performance. Stress can be divided into two categories which are compressive and tensile stress. Strain technology is capable to introduce stress to the CMOS devices. The strain technology can be developed by Silicon Nitride (Si3N4) capping layer, Silicide and Shallow Trench Isolation (STI). The paper discussed on the effect of strain technology on 140nm CMOS device performance focusing on threshold voltage and drain current parameters. ATHENA and ATLAS simulators were used to simulate the fabrication process and to characterize the electrical properties respectively. It can be concluded that STI is better compared to LOCOS for length gate below than 250nm devices. Compressive STI stress enhances by 13.8% PMOS performance while tensile Si3N4 capping layer improve by 1% NMOS performance. In addition CMOS with silicide module improve by 2.5% PMOS drain current.
format Article
author Zoolfakar, Ahmad Sabirin
Mohmad Tahiruddin, Noor Irmahani
Ismail, Lyly Nyl
author_facet Zoolfakar, Ahmad Sabirin
Mohmad Tahiruddin, Noor Irmahani
Ismail, Lyly Nyl
author_sort Zoolfakar, Ahmad Sabirin
title Modeling of “strain technology” on 140nm CMOS devices / Ahmad Sabirin Zoolfakar, Noor Irmahani Mohmad Tahiruddin and Lyly Nyl Ismail
title_short Modeling of “strain technology” on 140nm CMOS devices / Ahmad Sabirin Zoolfakar, Noor Irmahani Mohmad Tahiruddin and Lyly Nyl Ismail
title_full Modeling of “strain technology” on 140nm CMOS devices / Ahmad Sabirin Zoolfakar, Noor Irmahani Mohmad Tahiruddin and Lyly Nyl Ismail
title_fullStr Modeling of “strain technology” on 140nm CMOS devices / Ahmad Sabirin Zoolfakar, Noor Irmahani Mohmad Tahiruddin and Lyly Nyl Ismail
title_full_unstemmed Modeling of “strain technology” on 140nm CMOS devices / Ahmad Sabirin Zoolfakar, Noor Irmahani Mohmad Tahiruddin and Lyly Nyl Ismail
title_sort modeling of “strain technology” on 140nm cmos devices / ahmad sabirin zoolfakar, noor irmahani mohmad tahiruddin and lyly nyl ismail
publisher UiTM Press
publishDate 2009
url https://ir.uitm.edu.my/id/eprint/61856/1/61856.pdf
https://ir.uitm.edu.my/id/eprint/61856/
https://jeesr.uitm.edu.my/v1/
_version_ 1736837370005684224
score 13.211869

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