Double precision floating point unit using ISim simulator / Nurul Hidayah Maksom
This paper presents to design Verilog code double precision floating point unit using the arithmetic operation. A method for representation of double precision floating-point numbers with four common operations is proposed in this project. Sometimes the computer result of a calculation that reflects...
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| Format: | Student Project |
| Language: | English |
| Published: |
2012
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| Subjects: | |
| Online Access: | https://ir.uitm.edu.my/id/eprint/102905/1/102905.pdf https://ir.uitm.edu.my/id/eprint/102905/ |
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| Summary: | This paper presents to design Verilog code double precision floating point unit using the arithmetic operation. A method for representation of double precision floating-point numbers with four common operations is proposed in this project. Sometimes the computer result of a calculation that reflects some error was made. Possibly the magnitude of the result of a calculation was larger or smaller than this format would seem to be able to support. Possibly attempted to divide by zero and trying to represent zero. These issues is special cases of floating point numbers, specifically when the exponent field is all 1 bits (2047) or all 0 bits (O).Double precision floating point unit will divide into two numbers such as normalize and denormalize number to find out the implicit leading of the accuracy answer. The simple mathematical equation use to solve the various problem in computer design more accuracy. Simple operation equations with the 64 bits floating point were synthesized and analyze using Xilinx ISE software. Some areas of project are simulating Verilog code using ISim simulator to get the answer of operation from the wave shown. |
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