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Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi

This thesis presents the comparative study on 64-bit dynamic comparator using 0.18μm CMOS technology. The objective of this thesis is to study and compare the speed of the comparator using 0.5μm and 0.18μm technology and to compare the power consumption/dissipation for comparator in 0.5μm and 0.18μm...

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Main Author: Mohd Zaidi, Mohd Khushairi
Format: Thesis
Language:English
Published: 2013
Subjects:
Applications of electric power
Online Access:https://ir.uitm.edu.my/id/eprint/102889/1/102889.pdf
https://ir.uitm.edu.my/id/eprint/102889/
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spelling my.uitm.ir.1028892024-11-11T06:57:12Z https://ir.uitm.edu.my/id/eprint/102889/ Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi Mohd Zaidi, Mohd Khushairi Applications of electric power This thesis presents the comparative study on 64-bit dynamic comparator using 0.18μm CMOS technology. The objective of this thesis is to study and compare the speed of the comparator using 0.5μm and 0.18μm technology and to compare the power consumption/dissipation for comparator in 0.5μm and 0.18μm technology. Comparator is a device that compares two inputs and chooses the high/low or same value to be the output depends on the device application. The tools used in designing comparator are SILVACO GATEWAY for schematic design. Result show that the power consumption are 3.81nW and the delay is 142.98ps. 2013 Thesis NonPeerReviewed text en https://ir.uitm.edu.my/id/eprint/102889/1/102889.pdf Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi. (2013) Degree thesis, thesis, Universiti Teknologi MARA (UiTM). <http://terminalib.uitm.edu.my/102889.pdf>
institution Universiti Teknologi Mara
building Tun Abdul Razak Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Mara
content_source UiTM Institutional Repository
url_provider http://ir.uitm.edu.my/
language English
topic Applications of electric power
spellingShingle Applications of electric power
Mohd Zaidi, Mohd Khushairi
Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi
description This thesis presents the comparative study on 64-bit dynamic comparator using 0.18μm CMOS technology. The objective of this thesis is to study and compare the speed of the comparator using 0.5μm and 0.18μm technology and to compare the power consumption/dissipation for comparator in 0.5μm and 0.18μm technology. Comparator is a device that compares two inputs and chooses the high/low or same value to be the output depends on the device application. The tools used in designing comparator are SILVACO GATEWAY for schematic design. Result show that the power consumption are 3.81nW and the delay is 142.98ps.
format Thesis
author Mohd Zaidi, Mohd Khushairi
author_facet Mohd Zaidi, Mohd Khushairi
author_sort Mohd Zaidi, Mohd Khushairi
title Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi
title_short Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi
title_full Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi
title_fullStr Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi
title_full_unstemmed Power efficient 64-BIT dynamic comparator using 0.18um technology / Mohd Khushairi Mohd Zaidi
title_sort power efficient 64-bit dynamic comparator using 0.18um technology / mohd khushairi mohd zaidi
publishDate 2013
url https://ir.uitm.edu.my/id/eprint/102889/1/102889.pdf
https://ir.uitm.edu.my/id/eprint/102889/
_version_ 1817847085227048960
score 13.223943

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