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A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar

An iterative mincut heunstic for partitioning networks is presented whose worst case computation time, per pass, grows linearly with the size of the network. In practice, only a very small number of passes are typicaUy needed. To deal with cells of various size , the algorithm progresses by moving o...

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Main Author: Omar, Burhanuddin
Format: Thesis
Language:English
Published: 1997
Online Access:https://ir.uitm.edu.my/id/eprint/101532/1/101532.pdf
https://ir.uitm.edu.my/id/eprint/101532/
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id my.uitm.ir.101532
record_format eprints
spelling my.uitm.ir.1015322024-09-14T07:46:42Z https://ir.uitm.edu.my/id/eprint/101532/ A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar Omar, Burhanuddin An iterative mincut heunstic for partitioning networks is presented whose worst case computation time, per pass, grows linearly with the size of the network. In practice, only a very small number of passes are typicaUy needed. To deal with cells of various size , the algorithm progresses by moving one cell at a time between the blocks of the partition while maintaining a desired based on the size of the blocks rather than the number of cells per block. The program is being develop using this algorithm. The evaluation and comparison also been carried out between this method and Kernighan-Lin method. 1997 Thesis NonPeerReviewed text en https://ir.uitm.edu.my/id/eprint/101532/1/101532.pdf A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar. (1997) Degree thesis, thesis, Universiti Teknologi MARA (UiTM).
institution Universiti Teknologi Mara
building Tun Abdul Razak Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Mara
content_source UiTM Institutional Repository
url_provider http://ir.uitm.edu.my/
language English
description An iterative mincut heunstic for partitioning networks is presented whose worst case computation time, per pass, grows linearly with the size of the network. In practice, only a very small number of passes are typicaUy needed. To deal with cells of various size , the algorithm progresses by moving one cell at a time between the blocks of the partition while maintaining a desired based on the size of the blocks rather than the number of cells per block. The program is being develop using this algorithm. The evaluation and comparison also been carried out between this method and Kernighan-Lin method.
format Thesis
author Omar, Burhanuddin
spellingShingle Omar, Burhanuddin
A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar
author_facet Omar, Burhanuddin
author_sort Omar, Burhanuddin
title A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar
title_short A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar
title_full A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar
title_fullStr A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar
title_full_unstemmed A study on the VLSI partitions: the implementation of Fiduccia-Mattheyses algorithm / Burhanuddin Omar
title_sort study on the vlsi partitions: the implementation of fiduccia-mattheyses algorithm / burhanuddin omar
publishDate 1997
url https://ir.uitm.edu.my/id/eprint/101532/1/101532.pdf
https://ir.uitm.edu.my/id/eprint/101532/
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score 13.211869

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