Smart arbitration system for multiprocessor AMBA interface in system on chip
This paper describes the efficient arbitration scheme of an interface that provides access by multiple AMBA processors to targets in SoC (System on the Chip). The arbiter receives requests from several processors and issues grant signals by using its internal arbitration...
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Conference or Workshop Item |
| Language: | English English |
| Published: |
IEEE
2021
|
| Subjects: | |
| Online Access: | http://irep.iium.edu.my/90599/1/09467244.pdf http://irep.iium.edu.my/90599/7/90599_Smart%20Arbitration%20System%20for%20Multiprocessor%20AMBA_schedule.pdf http://irep.iium.edu.my/90599/ https://ieeexplore-ieee-org.ezlib.iium.edu.my/document/9467244 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | This paper describes the efficient arbitration
scheme of an interface that provides access by multiple AMBA processors to targets in SoC (System
on the Chip). The arbiter receives requests from several processors and issues grant signals
by using its internal arbitration process to that processor allowed to get control
over the bus through the AHB interface. The interface is common for all the
accessing processors to decide who’s address, control signals, read data and write data to
access any specific targets out of many like RAM or registers or others. The HDL
modelling was done using Verilog HDL, a simulation by Cadence and Modelsim Simulator, and
hardware implementation using Xilinx Pegasus FPGA device. FPGA device is used for quick
implementation at its site without going foundry so that its hardware impact can be
sorted out. It can be implemented in ASIC (Application Specific Integrated Circuit) too, for
low gate count, higher speed low power for any SoC. The processor interface is the
significant and critical block determining the controlling mechanism to provide
processor access inside slave targets inside any system. A single processor was used
previously. But modern systems are very sophisticated in respect of speed, complexity and
size. To op the need for a complex system, multiple processors are put in Chip
and the arbitration system’s job is to figure out efficient access by several
processors. This research addresses efficient multiprocessor access by implementing a
smart arbitration mechanism to provide grants to the processors. AMBA bus protocol is
the industry-standard protocol and very convenient to use with any off the shelf macro
available for the high tech industry. |
|---|