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Hardware modeling of binary coded decimal adder in field programmable gate array

There are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research....

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Main Authors: Ibrahimy, Muhammad Ibn, Ahsan, Md. Rezwanul, Soeroso, Iksannurazmi Bambang
Format: Article
Language:English
Published: Science Publications 2013
Subjects:
T Technology (General)
Online Access:http://irep.iium.edu.my/30536/1/PDF_ajassp.2013.466.477.pdf
http://irep.iium.edu.my/30536/
http://thescipub.com/ajas.toc
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spelling my.iium.irep.305362013-07-11T03:55:03Z http://irep.iium.edu.my/30536/ Hardware modeling of binary coded decimal adder in field programmable gate array Ibrahimy, Muhammad Ibn Ahsan, Md. Rezwanul Soeroso, Iksannurazmi Bambang T Technology (General) There are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, Carry Look Ahead (CLA) and Ripple Carry (RC) adder have been studied, designed and compared in terms of area consumption and time requirement. The simulation results show that the CLA adder performs faster with optimized area consumption. Verilog Hardware Description Language (HDL) is used for designing the model with the help of Altera Quartus II Electronic Design Automation (EDA) tool. EDA synthesis tools make it easy to develop an HDL model and which can be synthesized into target-specific architectures. Whereas, the HDL based modeling provides shorter development phases with continuous testing and verification of the system performance and behavior. After successful functional and timing simulations of the CLA based BCD adder, the design has been downloaded to physical FPGA device. For FPGA implementation, the Altera DE2 board has been used which contains Altera Cyclone II 2C35 FPGA device. Science Publications 2013 Article REM application/pdf en http://irep.iium.edu.my/30536/1/PDF_ajassp.2013.466.477.pdf Ibrahimy, Muhammad Ibn and Ahsan, Md. Rezwanul and Soeroso, Iksannurazmi Bambang (2013) Hardware modeling of binary coded decimal adder in field programmable gate array. American Journal of Applied Sciences, 10 (5). pp. 466-477. ISSN 1546-9239 http://thescipub.com/ajas.toc doi:10.3844/ajassp.2013.466.477
institution Universiti Islam Antarabangsa Malaysia
building IIUM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider International Islamic University Malaysia
content_source IIUM Repository (IREP)
url_provider http://irep.iium.edu.my/
language English
topic T Technology (General)
spellingShingle T Technology (General)
Ibrahimy, Muhammad Ibn
Ahsan, Md. Rezwanul
Soeroso, Iksannurazmi Bambang
Hardware modeling of binary coded decimal adder in field programmable gate array
description There are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, Carry Look Ahead (CLA) and Ripple Carry (RC) adder have been studied, designed and compared in terms of area consumption and time requirement. The simulation results show that the CLA adder performs faster with optimized area consumption. Verilog Hardware Description Language (HDL) is used for designing the model with the help of Altera Quartus II Electronic Design Automation (EDA) tool. EDA synthesis tools make it easy to develop an HDL model and which can be synthesized into target-specific architectures. Whereas, the HDL based modeling provides shorter development phases with continuous testing and verification of the system performance and behavior. After successful functional and timing simulations of the CLA based BCD adder, the design has been downloaded to physical FPGA device. For FPGA implementation, the Altera DE2 board has been used which contains Altera Cyclone II 2C35 FPGA device.
format Article
author Ibrahimy, Muhammad Ibn
Ahsan, Md. Rezwanul
Soeroso, Iksannurazmi Bambang
author_facet Ibrahimy, Muhammad Ibn
Ahsan, Md. Rezwanul
Soeroso, Iksannurazmi Bambang
author_sort Ibrahimy, Muhammad Ibn
title Hardware modeling of binary coded decimal adder in field programmable gate array
title_short Hardware modeling of binary coded decimal adder in field programmable gate array
title_full Hardware modeling of binary coded decimal adder in field programmable gate array
title_fullStr Hardware modeling of binary coded decimal adder in field programmable gate array
title_full_unstemmed Hardware modeling of binary coded decimal adder in field programmable gate array
title_sort hardware modeling of binary coded decimal adder in field programmable gate array
publisher Science Publications
publishDate 2013
url http://irep.iium.edu.my/30536/1/PDF_ajassp.2013.466.477.pdf
http://irep.iium.edu.my/30536/
http://thescipub.com/ajas.toc
_version_ 1643609892868587520
score 13.211869

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