Design of a current comparator for quaternary multi valued analog to digital converter
A low-power quaternary comparator circuit using current-mode CMOS multiple-valued logic (MVL) circuits has been presented in this paper. Existing MVL comparator circuits consume high power. The circuit presented in this paper has been shown low power digital output. It has been simulated with PSPICE...
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| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2011
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/11857/1/Design_of_a_current_comparator_for_quaternary_multi_valued_analog_to_digital_converter.pdf http://irep.iium.edu.my/11857/ http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6088321&tag=1 |
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