Fairness in multiprocessor hardware access to system-on-chip
This paper addresses the acces of multiprocessors into numerous blocks within an SoC (System-on-Chip). The process by which the processor, internal or external, gains the right to access different blocks on an ASIC is first they have issue an access to request a choice-making main block that de...
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2022
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| Online Access: | http://irep.iium.edu.my/100749/1/100749_Fairness%20in%20multiprocessor%20hardware.pdf http://irep.iium.edu.my/100749/ https://ieeexplore.ieee.org/document/9915675 |
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my.iium.irep.1007492022-10-20T03:23:37Z http://irep.iium.edu.my/100749/ Fairness in multiprocessor hardware access to system-on-chip Rokon, M. I. R. Motakabber, S. M. A. Alam, A. H. M. Zahirul Habaebi, Mohamed Hadi Matin, M. A, TK7885 Computer engineering This paper addresses the acces of multiprocessors into numerous blocks within an SoC (System-on-Chip). The process by which the processor, internal or external, gains the right to access different blocks on an ASIC is first they have issue an access to request a choice-making main block that determines the status of the grant to the processor. In a simple ASIC, a single processor is ideal enough to fulfil all itsd access needs, but dealing with a very complex and large ASIC requires several processors. In this type of case, it is difficult to design and extend the selection block that determines the access of the multi processor to the chip. There are many algorithms to adapt to this initiative. They all have strengths and weaknesses. The purpose of this research paper is to improve strengths and keep weaknesses away. The hardware RTL modelling of the proposed design has been done using Verilog HDL and verified by Verilog test bench. then implemented by the Xilinx Pegasus FPGA device. The Modelsim simulator and Cadence simulator, are both used simultaneously for simulation. The proposed system block can be assembled at any SoC and fabricated from a foundry. Xilinx Pegasus FPGA has been used to implement the hardware in this study and the results show good consistency with expectations and theories. IEEE 2022-08-08 Conference or Workshop Item PeerReviewed application/pdf en http://irep.iium.edu.my/100749/1/100749_Fairness%20in%20multiprocessor%20hardware.pdf Rokon, M. I. R. and Motakabber, S. M. A. and Alam, A. H. M. Zahirul and Habaebi, Mohamed Hadi and Matin, M. A, (2022) Fairness in multiprocessor hardware access to system-on-chip. In: IEEE 5th International Symposium in Robotics and Manufacturing Automation, 6 - 8 August 2022, Malacca, Malaysia. https://ieeexplore.ieee.org/document/9915675 10.1109/ROMA55875.2022.9915675 |
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TK7885 Computer engineering |
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TK7885 Computer engineering Rokon, M. I. R. Motakabber, S. M. A. Alam, A. H. M. Zahirul Habaebi, Mohamed Hadi Matin, M. A, Fairness in multiprocessor hardware access to system-on-chip |
| description |
This paper addresses the acces of multiprocessors
into numerous blocks within an SoC (System-on-Chip). The
process by which the processor, internal or external, gains the
right to access different blocks on an ASIC is first they have
issue an access to request a choice-making main block that
determines the status of the grant to the processor. In a simple
ASIC, a single processor is ideal enough to fulfil all itsd access
needs, but dealing with a very complex and large ASIC requires
several processors. In this type of case, it is difficult to design
and extend the selection block that determines the access of the
multi processor to the chip. There are many algorithms to adapt
to this initiative. They all have strengths and weaknesses. The
purpose of this research paper is to improve strengths and keep
weaknesses away. The hardware RTL modelling of the proposed
design has been done using Verilog HDL and verified by Verilog
test bench. then implemented by the Xilinx Pegasus FPGA
device. The Modelsim simulator and Cadence simulator, are
both used simultaneously for simulation. The proposed system
block can be assembled at any SoC and fabricated from a
foundry. Xilinx Pegasus FPGA has been used to implement the
hardware in this study and the results show good consistency
with expectations and theories. |
| format |
Conference or Workshop Item |
| author |
Rokon, M. I. R. Motakabber, S. M. A. Alam, A. H. M. Zahirul Habaebi, Mohamed Hadi Matin, M. A, |
| author_facet |
Rokon, M. I. R. Motakabber, S. M. A. Alam, A. H. M. Zahirul Habaebi, Mohamed Hadi Matin, M. A, |
| author_sort |
Rokon, M. I. R. |
| title |
Fairness in multiprocessor hardware access
to system-on-chip |
| title_short |
Fairness in multiprocessor hardware access
to system-on-chip |
| title_full |
Fairness in multiprocessor hardware access
to system-on-chip |
| title_fullStr |
Fairness in multiprocessor hardware access
to system-on-chip |
| title_full_unstemmed |
Fairness in multiprocessor hardware access
to system-on-chip |
| title_sort |
fairness in multiprocessor hardware access
to system-on-chip |
| publisher |
IEEE |
| publishDate |
2022 |
| url |
http://irep.iium.edu.my/100749/1/100749_Fairness%20in%20multiprocessor%20hardware.pdf http://irep.iium.edu.my/100749/ https://ieeexplore.ieee.org/document/9915675 |
| _version_ |
1748180277705834496 |
| score |
13.211869 |