NMOS DEVICE OPTIMIZATION AND FABRICATION USING ATHENA & ATLAS SIMULATION SOFTWARE
Experiment has proven that NMOS performs better than PMOS due to higher drive current, higher mobility, easier to implement scaling technology and low power consumption. However, there is still room for further optimization as the technology trend for the miniaturization ofNMOS and integrated dev...
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| Main Author: | |
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| Format: | Final Year Project |
| Language: | English |
| Published: |
Universiti Teknologi Petronas
2004
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| Online Access: | http://utpedia.utp.edu.my/7529/1/2004%20-%20NMOS%20DEVICE%20OPTIMIZATION%20AND%20FABRICATION%20USING%20ATHENA%20%26%20ATLAS%20SIMULATION%20SOFTWARE.pdf http://utpedia.utp.edu.my/7529/ |
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| Summary: | Experiment has proven that NMOS performs better than PMOS due to higher drive
current, higher mobility, easier to implement scaling technology and low power
consumption. However, there is still room for further optimization as the technology
trend for the miniaturization ofNMOS and integrated devices continue to grow. In
this project, several objectives have been outlined to be completed within 2 semester
period. These include detailed understanding of fabrication aspect and NMOS
properties, optimizing NMOS by reducing threshold voltage, minimizing off-stage
leakage, reducing gate length, increasing switching speed and designing a mixed
mode circuit.
However, the cost required to perform experimental analysis and optimization of
semiconductor devices using fabrication process can be very expensive especially
when involving purchase of expensive electrical testing equipment. Thus, it is
recommended to perform optimization and analysis using simulation. One ofthe best
device process and simulation tool is Silvaco ATHENA & ATLAS simulation
software. It provides user with various capability in process and electrical testing.
After manipulating and improving process parameters, the optimized device has
recorded significant improvement over the predecessor. Optimizations include better
threshold voltage extraction (0.2v), drain current rise beyond pinch off, better drain
current extraction, higher switching speed at 2Ghz, better device structure after ion
implantation due to tilted implantation, lower off-stage leakage current
(1.2589 x 10' A/um) and minimization ofjunction breakdown effect. |
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