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DESIGN AND IMPLEMENTATION OF VLSI BASED HARDWARE ACCELERATORS FOR REAL TIME VIDEO IMAGE PROCESSING

Video image processing hardware implementation is continually driven to achieve high performance e.g. high resolution, less power consumption, high throughput and better image quality. However, the improvement has not achieved the required performance to support demanding complex computation a...

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Main Author: YASRI, INDRA
Format: Thesis
Language:English
Published: 2012
Subjects:
Instrumentation and Control
Online Access:http://utpedia.utp.edu.my/21630/1/2012%20-ELECTRICAL%20%26%20ELECTRONIC%20-%20DESIGN%20AND%20IMPLEMENTATION%20OF%20VLSI%20BASED%20HARDWARE%20ACCELERATORS%20FOR%20REAL%20TIME%20VIDEO%20IMAGE%20PROCESSING%20-%20INDRA%20YASRI.pdf
http://utpedia.utp.edu.my/21630/
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spelling my-utp-utpedia.216302021-09-23T09:58:47Z http://utpedia.utp.edu.my/21630/ DESIGN AND IMPLEMENTATION OF VLSI BASED HARDWARE ACCELERATORS FOR REAL TIME VIDEO IMAGE PROCESSING YASRI, INDRA Instrumentation and Control Video image processing hardware implementation is continually driven to achieve high performance e.g. high resolution, less power consumption, high throughput and better image quality. However, the improvement has not achieved the required performance to support demanding complex computation and large data transfer in application such as video surveillance and telemedicine on portable devices which require real time performance and with high data integrity. This work proposes low memory bandwidth access within edge detection hardware accelerator design to achieve real time performance of video image processing application in portable device. An enhanced parallel and pipeline technique is utilized to perform transfer data between memory and computation part and leading towards memory bandwidth reduction to achieve real time performance. The hardware accelerator edge detection design is integrated with clock divider, accelerator control, memory access controller, memory access register, address counter, address decoder and acknowledge generator. The design is compatible with standard interfacing of embedded processor system. It includes the significant components in embedded processor system design such as address decoder and address counter. These two components are involved in controlling base address registers and address offset counters for the original and derivative images, respectively. The hardware accelerator edge detection designs are implemented on Altera Stratix III DSP development board and enables application of co-processor without requiring new application specific digital signal processor. The embedded video image processing with the integrated hardware accelerator edge detection co-processor was integrated with Altera Quartus System-On- a�Programmable-Chip (SOPC). The implementation result shows a field programmable gate arrays (FPGAs) acting as co-processor platforms for user defined co-processor, with real time performance at a frame rate of 30 fps with a resolution of 720 x 480. The parallel and pipeline technique are utilized in memory access, resulting more than 70% memory bandwidth reduction. 2012-01 Thesis NonPeerReviewed application/pdf en http://utpedia.utp.edu.my/21630/1/2012%20-ELECTRICAL%20%26%20ELECTRONIC%20-%20DESIGN%20AND%20IMPLEMENTATION%20OF%20VLSI%20BASED%20HARDWARE%20ACCELERATORS%20FOR%20REAL%20TIME%20VIDEO%20IMAGE%20PROCESSING%20-%20INDRA%20YASRI.pdf YASRI, INDRA (2012) DESIGN AND IMPLEMENTATION OF VLSI BASED HARDWARE ACCELERATORS FOR REAL TIME VIDEO IMAGE PROCESSING. PhD thesis, Universiti Teknologi PETRONAS.
institution Universiti Teknologi Petronas
building UTP Resource Centre
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Petronas
content_source UTP Electronic and Digitized Intellectual Asset
url_provider http://utpedia.utp.edu.my/
language English
topic Instrumentation and Control
spellingShingle Instrumentation and Control
YASRI, INDRA
DESIGN AND IMPLEMENTATION OF VLSI BASED HARDWARE ACCELERATORS FOR REAL TIME VIDEO IMAGE PROCESSING
description Video image processing hardware implementation is continually driven to achieve high performance e.g. high resolution, less power consumption, high throughput and better image quality. However, the improvement has not achieved the required performance to support demanding complex computation and large data transfer in application such as video surveillance and telemedicine on portable devices which require real time performance and with high data integrity. This work proposes low memory bandwidth access within edge detection hardware accelerator design to achieve real time performance of video image processing application in portable device. An enhanced parallel and pipeline technique is utilized to perform transfer data between memory and computation part and leading towards memory bandwidth reduction to achieve real time performance. The hardware accelerator edge detection design is integrated with clock divider, accelerator control, memory access controller, memory access register, address counter, address decoder and acknowledge generator. The design is compatible with standard interfacing of embedded processor system. It includes the significant components in embedded processor system design such as address decoder and address counter. These two components are involved in controlling base address registers and address offset counters for the original and derivative images, respectively. The hardware accelerator edge detection designs are implemented on Altera Stratix III DSP development board and enables application of co-processor without requiring new application specific digital signal processor. The embedded video image processing with the integrated hardware accelerator edge detection co-processor was integrated with Altera Quartus System-On- a�Programmable-Chip (SOPC). The implementation result shows a field programmable gate arrays (FPGAs) acting as co-processor platforms for user defined co-processor, with real time performance at a frame rate of 30 fps with a resolution of 720 x 480. The parallel and pipeline technique are utilized in memory access, resulting more than 70% memory bandwidth reduction.
format Thesis
author YASRI, INDRA
author_facet YASRI, INDRA
author_sort YASRI, INDRA
title DESIGN AND IMPLEMENTATION OF VLSI BASED HARDWARE ACCELERATORS FOR REAL TIME VIDEO IMAGE PROCESSING
title_short DESIGN AND IMPLEMENTATION OF VLSI BASED HARDWARE ACCELERATORS FOR REAL TIME VIDEO IMAGE PROCESSING
title_full DESIGN AND IMPLEMENTATION OF VLSI BASED HARDWARE ACCELERATORS FOR REAL TIME VIDEO IMAGE PROCESSING
title_fullStr DESIGN AND IMPLEMENTATION OF VLSI BASED HARDWARE ACCELERATORS FOR REAL TIME VIDEO IMAGE PROCESSING
title_full_unstemmed DESIGN AND IMPLEMENTATION OF VLSI BASED HARDWARE ACCELERATORS FOR REAL TIME VIDEO IMAGE PROCESSING
title_sort design and implementation of vlsi based hardware accelerators for real time video image processing
publishDate 2012
url http://utpedia.utp.edu.my/21630/1/2012%20-ELECTRICAL%20%26%20ELECTRONIC%20-%20DESIGN%20AND%20IMPLEMENTATION%20OF%20VLSI%20BASED%20HARDWARE%20ACCELERATORS%20FOR%20REAL%20TIME%20VIDEO%20IMAGE%20PROCESSING%20-%20INDRA%20YASRI.pdf
http://utpedia.utp.edu.my/21630/
_version_ 1739832892347908096
score 13.211869

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