Cover Image

Front end design (logic synthesis) of Risc-V processor using design compiler

Modern microprocessors depend on Design Compiler's logic synthesis of RISC-V processor Front-Ends. This study examines the synthesis process for a 14nm, 32nm, or 90nm RISC-V processor at clock periods from 0 to 5 nanoseconds. The analysis begins with design constraints, including clock frequenc...

Full description

Saved in:
Bibliographic Details
Main Author: Koay, Yenn Nee
Format: Final Year Project / Dissertation / Thesis
Published: 2023
Subjects:
T Technology (General)
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utar.edu.my/5964/1/Koay_Yenn_Nee_21AGM06716.pdf
http://eprints.utar.edu.my/5964/
Tags: Add Tag
No Tags, Be the first to tag this record!
id my-utar-eprints.5964
record_format eprints
spelling my-utar-eprints.59642024-01-01T12:55:19Z Front end design (logic synthesis) of Risc-V processor using design compiler Koay, Yenn Nee T Technology (General) TK Electrical engineering. Electronics Nuclear engineering Modern microprocessors depend on Design Compiler's logic synthesis of RISC-V processor Front-Ends. This study examines the synthesis process for a 14nm, 32nm, or 90nm RISC-V processor at clock periods from 0 to 5 nanoseconds. The analysis begins with design constraints, including clock frequency, area limits, and timing requirements for each technological node. The Design Compiler tool converts the Register Transfer Level (RTL) description of the RISC-V processor into a gate-level netlist. The design's applicability to 14nm, 32nm, and 90nm process nodes is assessed during synthesis by linking technology libraries. After synthesizing designs, performance indicators like timing closure, clock period needs, and slack margins across technology nodes are analyzed. To understand the processor's power consumption, power analysis is done at different clock intervals. To optimize designs at each technological node, processor area consumption is analyzed. The research examines 14nm, 32nm, and 90nm front-end design performances using clock durations from 0 to 5 nanoseconds. These different manufacturing technologies and operating circumstances provide vital insights about the processor's performance, power efficiency, and space usage. With this knowledge, designers can choose technology, clock frequency, and architectural changes to suit future computing system demands. This research helps designers construct high-performance, energy efficient, area-optimized RISC-V processors that are adaptable to different technology nodes and clock periods. The study advances front-end design in microprocessor development, enabling the design of cutting-edge processors that excel across varied technology landscapes and operating scenarios. 2023-05 Final Year Project / Dissertation / Thesis NonPeerReviewed application/pdf http://eprints.utar.edu.my/5964/1/Koay_Yenn_Nee_21AGM06716.pdf Koay, Yenn Nee (2023) Front end design (logic synthesis) of Risc-V processor using design compiler. Master dissertation/thesis, UTAR. http://eprints.utar.edu.my/5964/
institution Universiti Tunku Abdul Rahman
building UTAR Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tunku Abdul Rahman
content_source UTAR Institutional Repository
url_provider http://eprints.utar.edu.my
topic T Technology (General)
TK Electrical engineering. Electronics Nuclear engineering
spellingShingle T Technology (General)
TK Electrical engineering. Electronics Nuclear engineering
Koay, Yenn Nee
Front end design (logic synthesis) of Risc-V processor using design compiler
description Modern microprocessors depend on Design Compiler's logic synthesis of RISC-V processor Front-Ends. This study examines the synthesis process for a 14nm, 32nm, or 90nm RISC-V processor at clock periods from 0 to 5 nanoseconds. The analysis begins with design constraints, including clock frequency, area limits, and timing requirements for each technological node. The Design Compiler tool converts the Register Transfer Level (RTL) description of the RISC-V processor into a gate-level netlist. The design's applicability to 14nm, 32nm, and 90nm process nodes is assessed during synthesis by linking technology libraries. After synthesizing designs, performance indicators like timing closure, clock period needs, and slack margins across technology nodes are analyzed. To understand the processor's power consumption, power analysis is done at different clock intervals. To optimize designs at each technological node, processor area consumption is analyzed. The research examines 14nm, 32nm, and 90nm front-end design performances using clock durations from 0 to 5 nanoseconds. These different manufacturing technologies and operating circumstances provide vital insights about the processor's performance, power efficiency, and space usage. With this knowledge, designers can choose technology, clock frequency, and architectural changes to suit future computing system demands. This research helps designers construct high-performance, energy efficient, area-optimized RISC-V processors that are adaptable to different technology nodes and clock periods. The study advances front-end design in microprocessor development, enabling the design of cutting-edge processors that excel across varied technology landscapes and operating scenarios.
format Final Year Project / Dissertation / Thesis
author Koay, Yenn Nee
author_facet Koay, Yenn Nee
author_sort Koay, Yenn Nee
title Front end design (logic synthesis) of Risc-V processor using design compiler
title_short Front end design (logic synthesis) of Risc-V processor using design compiler
title_full Front end design (logic synthesis) of Risc-V processor using design compiler
title_fullStr Front end design (logic synthesis) of Risc-V processor using design compiler
title_full_unstemmed Front end design (logic synthesis) of Risc-V processor using design compiler
title_sort front end design (logic synthesis) of risc-v processor using design compiler
publishDate 2023
url http://eprints.utar.edu.my/5964/1/Koay_Yenn_Nee_21AGM06716.pdf
http://eprints.utar.edu.my/5964/
_version_ 1787140944258138112
score 13.211869

Similar Items