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Algorithm optimization and low cost bit-serial architecture design for integer-pixel and sub-pixel motion estimation in H.264/AVC / Mohammad Reza Hosseiny Fatemi by Hosseiny Fatemi, Mohammad Reza

Published 2012
“…For the hardware architecture design, we choose bit-serial structure for implementing our algorithm to benefit from its advantages. Moreover, we use SAD truncation, reusability, source sharing, and power saving techniques in our architecture, which lead to area saving and power consumption reduction. …”

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