Search Results - "Test pattern generations"

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  1. 1
    Scan Test Coverage Improvement Via Automatic Test Pattern Generation (Atpg) Tool Configuration

    Scan Test Coverage Improvement Via Automatic Test Pattern Generation (Atpg) Tool Configuration by Salehuddin, Muhammad Redzwan

    Published 2017
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  2. 2
    LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage

    LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage by Islam S.Z., Ali M.A.M.

    Published 2023
    Conference paper
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  3. 3
    Deterministic Automatic Test Pattern Generation for Built-In Self Test System

    Deterministic Automatic Test Pattern Generation for Built-In Self Test System by Mohammed Khalid, Muhammad Nazir

    Published 2006
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  4. 4
    A procedure of a test pattern generation for CMOS operational amplifier based on the inverting amplifier

    A procedure of a test pattern generation for CMOS operational amplifier based on the inverting amplifier by Abdul Halin, Izhal, Suparjo, Bambang Sunaryo, Wan Hasan, Wan Zuha, Wagiran, Rahman, Mohd Sidek, Roslina

    Published 2002
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  5. 5
    Design built-in self-test for control sequencer circuit using xilinx

    Design built-in self-test for control sequencer circuit using xilinx by Mohamed Isa, Nurul Aini

    Published 2004
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  6. 6
    Development of high speed booth multiplier with optimized stuck-at fault implementation

    Development of high speed booth multiplier with optimized stuck-at fault implementation by Mohammed Khalid, Muhammad Nazir, Wan Hasan, Wan Zuha, Sulaiman, Nasri, Wagiran, Rahman

    Published 2002
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  7. 7
    High degree of testability using full scan chain and ATPG-An industrial perspective

    High degree of testability using full scan chain and ATPG-An industrial perspective by Mamun, Ibne Reaz, Lee, W. F., Hamid, N. H., Lo, H. H., Ali Yeon, Mohd Shakaff, Prof. Dr.

    Published 2010
    Subjects: “…Automatic test pattern generation…”
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  8. 8
    Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system

    Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system by Islam S.Z., Ali M.A.M.

    Published 2023
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  9. 9
    Design of large built-in self-test programmable logic arrays

    Design of large built-in self-test programmable logic arrays by Zahari Mohamed Darus, Iftekhar Ahmed

    Published 1993
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  10. 10
    A study on signature analyzer for design for test (DFT)

    A study on signature analyzer for design for test (DFT) by A'ain, Abu Khari, Lim, C. T., Kok, Hong Ng, Sheng, Kwang Ng, Liew, Eng Yew

    Published 2004
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  11. 11
    Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems

    Delay Fault Modelling/Simulation using VHDL-AMS in Multi Vdd Systems by Zain Ali, Noohul Basheer, Mark, Zwolinski, Ahmadi, Arash

    Published 2008
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  12. 12
    Design Methodology to Achieve Good Testability of VLSI Chips: An Industrial Perspective

    Design Methodology to Achieve Good Testability of VLSI Chips: An Industrial Perspective by Lo, Hai Hiung, Lee, Weng Fook, Reaz, B. I., Hamid, Nor Hisham

    Published 2009
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  13. 13
    Built in self test for RAM using VHDL

    Built in self test for RAM using VHDL by Husin, M.H., Leong, S.Y., Sabri, M.F.M.

    Published 2013
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  14. 14
    High Degree of Testability Using Full Scan Chain and ATPG: An Industrial Perspective

    High Degree of Testability Using Full Scan Chain and ATPG: An Industrial Perspective by B. I. Reaz, Mamun, F. Lee, Weng, Hamid, Nor Hisham, Hai, H. Lo, Y. M. Shakaff, Ali

    Published 2009
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  15. 15
    Automatic generation of user-defined test algorithm description file for memory BIST implementation

    Automatic generation of user-defined test algorithm description file for memory BIST implementation by Hussin, Razaidi, Jidin, Aiman Zakwan, Loh, Wan Ying, Mispan, Mohd Syafiq, Lee, Weng Fook

    Published 2022
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  16. 16
    High degree of testability using full scan chain and ATPG-An industrial perspective

    High degree of testability using full scan chain and ATPG-An industrial perspective by M.B.I., Reaz, W.F., Lee, N.H., Hamid, H.H., Lo, A.Y.M., Shakaff

    Published 2009
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