Search Results - "Gate structure"

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  1. 1
    Fabrication Of Submicron HEMT Mushroom Gate Structure Using Electron Beam Lithography And Its Characterization

    Fabrication Of Submicron HEMT Mushroom Gate Structure Using Electron Beam Lithography And Its Characterization by Yusof, Ashaari

    Published 2008
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  2. 2
    Design, fabrication and characterization of GaAs-based interdigital-gated HEMT devices for solid-state THz wave amplifiers

    Design, fabrication and characterization of GaAs-based interdigital-gated HEMT devices for solid-state THz wave amplifiers by Hashim, Abdul Manaf, Kasai, Seiya, Lizuki, Kouichi, Hashizume, Tamotsu, Hasegawa, Hideki

    Published 2007
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  3. 3
    Novel structure of GaAs-based interdigital-gated HEMT plasma devices for solid-state THz wave amplifier

    Novel structure of GaAs-based interdigital-gated HEMT plasma devices for solid-state THz wave amplifier by Hashim, Abdul Manaf, Kasai , Seiya, Iizuki, Kouichi, Hashizume, Tamotsu, Hasegawa, Hideki

    Published 2007
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  4. 4
    Cobalt silicide and titanium silicide effects on nano devices

    Cobalt silicide and titanium silicide effects on nano devices by Elgomati H.A., Majlis B.Y., Salehuddin F., Ahmad I., Zaharim A., Hamid F.A.

    Published 2023
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  5. 5
    Row decoder and row driver custom design using 0.18 um CMOS technology / Md Aizuddin Rosdan

    Row decoder and row driver custom design using 0.18 um CMOS technology / Md Aizuddin Rosdan by Rosdan, Md Aizuddin

    Published 2013
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  6. 6
    Nanoscale patterning by AFM lithography and its application on the fabrication of silicon nanowire devices

    Nanoscale patterning by AFM lithography and its application on the fabrication of silicon nanowire devices by Sabar D. Hutagalung, Kam, Chung Lew, Darsono, Teguh

    Published 2014
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  7. 7
    NUMERICAL VIBRATION ANALYSIS OF THE DAM SECTOR GATE STRUCTURE WITH CONSIDERATION TO MATERIAL DEGRADATION CHARACTERISTICS

    NUMERICAL VIBRATION ANALYSIS OF THE DAM SECTOR GATE STRUCTURE WITH CONSIDERATION TO MATERIAL DEGRADATION CHARACTERISTICS by Ghazali M.H.M., Mazlan A.Z.A., Azman M.A., Zawawi M.H.

    Published 2023
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  8. 8
    Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime

    Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime by Saad, Ismail, Sulaiman, Ima, Ismail, Razali

    Published 2008
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  9. 9
    Design of voltage controlled oscillator (VCO) for ultra wideband (UWB) CMOS frequency synthesizer

    Design of voltage controlled oscillator (VCO) for ultra wideband (UWB) CMOS frequency synthesizer by M., Awan, S., Zafar, T.Z.A., Zulkifli

    Published 2007
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  10. 10
    5-GHz low-phase noise quadrature VCO in 0.13-μm RF CMOS process technology

    5-GHz low-phase noise quadrature VCO in 0.13-μm RF CMOS process technology by M., Awan, S., Zafar, T.Z.A., Zulkifli

    Published 2009
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  11. 11
    Effects of post-deposition annealing temperatures on the composition of interfacial layer at germanium (Ge) /aluminium oxide (Al2O3)

    Effects of post-deposition annealing temperatures on the composition of interfacial layer at germanium (Ge) /aluminium oxide (Al2O3) by Siti Kudnie Sahari, Nik Amni Fathi Nik Zaini Fathi, Azrul Azlan Hamzah, Norsuzailina Mohamed Sutan, Zaidi Embong, Suhana Mohamed Sultan, Muhammad Kashif, Marini Sawawi, Hasanah, Lilik, Rohana Sapawi, Kuryati Kipli, Abdul Rahman Kram, Nazreen Junaidi

    Published 2019
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  12. 12
    Process Characterization of 32nm Semi Analytical Bilayer Graphene-based MOSFET

    Process Characterization of 32nm Semi Analytical Bilayer Graphene-based MOSFET by Noor Faizah Z.A., Ahmad I., Ker P.J., Menon P.S.

    Published 2023
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  13. 13
    Threshold voltage and leakage current variability on process parameter in a 22nm PMOS Device

    Threshold voltage and leakage current variability on process parameter in a 22nm PMOS Device by Afifah Maheran A.H., Menon P.S., Ahmad I., Noor Faizah Z.A., Mohd Zain A.S., Salehuddin F., Sayed N.M.

    Published 2023
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  14. 14
    Design Consideration And Impact Of Gate Length Variation On Junctionless Strained Double Gate MOSFET

    Design Consideration And Impact Of Gate Length Variation On Junctionless Strained Double Gate MOSFET by Kaharudin, Khairil Ezwan, Salehuddin, Fauziyah, Roslan, Ameer Farhan, Mohammed Napiah, Zul Atfyi Fauzan, Mohd Zain, Anis Suhaila

    Published 2019
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  15. 15
    Taguchi method statistical analysis on characterization and optimization of 18- nm double gate MOSFETs

    Taguchi method statistical analysis on characterization and optimization of 18- nm double gate MOSFETs by Abdul Hamid, Afifah Maheran, Mogan, Pritigavane, Mohd Nizam, Nur Hazwani Naili, Salehuddin, Fauziyah, Sabani, Norhayati

    Published 2024
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  16. 16
    Effects of Post-Deposition Annealing Temperatures on the Composition of Interfacial Layer at Germanium (Ge) /Aluminium Oxide (Al2 O3 ) (Kesan Suhu Penyepuhlindapan Pasca Pemendapan ke atas Komposisi Antara Muka Lapisan Oksida Germanium (Ge)/Aluminium (Al2 O3 ))

    Effects of Post-Deposition Annealing Temperatures on the Composition of Interfacial Layer at Germanium (Ge) /Aluminium Oxide (Al2 O3 ) (Kesan Suhu Penyepuhlindapan Pasca Pemendapa... by Siti Kudnie, Sahari, Nik Amni Fathi, Nik Zaini Fathi, Azrul Azlan, Hamzah, Norsuzailina, Mohamed Sutan, Zaidi, Embong, Suhana, Muhamed Sultan, Muhammad, Kashif, Marini, Sawawi, Lilik, Hasanah, Rohana, Sapawi, Kuryati, Kipli, Abdul Rahman, Kram, Nazreen, Junaidi

    Published 2019
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  17. 17
    Development of process parameters for 22 nm PMOS using 2-D analytical modeling

    Development of process parameters for 22 nm PMOS using 2-D analytical modeling by Maheran A.H.A., Menon P.S., Ahmad I., Shaari S., Faizah Z.A.N.

    Published 2023
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  18. 18
    Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method

    Process parameter optimisation for minimum leakage current in a 22nm p-type MOSFET using Taguchi method by Afifah Maheran A.H., Menon P.S., Ahmad I., Salehuddin F., Mohd Zain A.S.

    Published 2023
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  19. 19
    Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.

    Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method. by Afifah Maheran A.H., Firhat E.N., Salehuddin F., Mohd Zain A.S., Ahmad I., Noor Faizah Z.A., Menon P.S., Elgomati H.A., Roslan A.F.

    Published 2023
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  20. 20
    Rotated majority gate-based 2n-bit full adder design in quantum-dot cellular automata nanotechnology

    Rotated majority gate-based 2n-bit full adder design in quantum-dot cellular automata nanotechnology by Kassa, S., Gupta, P., Kumar, M., Stephan, T., Kannan, R.

    Published 2021
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