Implementing digital finite impulse response filter using FPGA
This paper describes the design of Transposed Form FIR filter implemented in the Spartan-II and Virtex-E family of FPGAs. The design is an 8-tap filter based on 16-bit input samples and 14-bit signed coefficients.The basic building blocks of the filter are KCMs, Adders, Registers, and a delay-locked...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Language: | en |
| Published: |
2007
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| Subjects: | |
| Online Access: | https://repo.uum.edu.my/id/eprint/4561/1/Im.pdf https://repo.uum.edu.my/id/eprint/4561/ http://dx.doi.org/10.1109/APACE.2007.4603854 |
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