Efficient accelerated simulation technique for packet switched networks : a buffer with two priority inputs
An Enhanced Traffic Aggregation (E_TA) technique for acceleration simulation of packet switched network is proposed. This technique simplifies the simulation model and improves the efficiency by using packet-train or packet rate source traffic with non FIFO scheduler in the buffer. The model employs...
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| Format: | Book Section |
| Language: | en |
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IEEE
2004
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| Online Access: | http://eprints.utm.my/9791/1/SHSAriffin2004_Efficient_accelerated_simulation_technique_for_packet.pdf http://eprints.utm.my/9791/ |
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| author | Ariffin, Sharifah H. S. Schormans, John A. |
| author_facet | Ariffin, Sharifah H. S. Schormans, John A. |
| author_sort | Ariffin, Sharifah H. S. |
| building | UTM Library |
| collection | Institutional Repository |
| content_provider | Universiti Teknologi Malaysia |
| content_source | UTM Institutional Repository |
| continent | Asia |
| country | Malaysia |
| description | An Enhanced Traffic Aggregation (E_TA) technique for acceleration simulation of packet switched network is proposed. This technique simplifies the simulation model and improves the efficiency by using packet-train or packet rate source traffic with non FIFO scheduler in the buffer. The model employs power law traffic which recently proved to be able to capture both long-range dependence and the burstiness of aggregate broadband network traffic. Our results show that using E_TA with FIFO scheduler simulation times can be reduced by 39%, and using E_TA with non FIFO scheduler by 83 %. |
| format | Book Section |
| id | my.utm.eprints-9791 |
| institution | Universiti Teknologi Malaysia |
| language | en |
| publishDate | 2004 |
| publisher | IEEE |
| record_format | eprints |
| spelling | my.utm.eprints-97912017-08-15T04:05:29Z http://eprints.utm.my/9791/ Efficient accelerated simulation technique for packet switched networks : a buffer with two priority inputs Ariffin, Sharifah H. S. Schormans, John A. TK Electrical engineering. Electronics Nuclear engineering An Enhanced Traffic Aggregation (E_TA) technique for acceleration simulation of packet switched network is proposed. This technique simplifies the simulation model and improves the efficiency by using packet-train or packet rate source traffic with non FIFO scheduler in the buffer. The model employs power law traffic which recently proved to be able to capture both long-range dependence and the burstiness of aggregate broadband network traffic. Our results show that using E_TA with FIFO scheduler simulation times can be reduced by 39%, and using E_TA with non FIFO scheduler by 83 %. IEEE 2004-06-20 Book Section PeerReviewed application/pdf en http://eprints.utm.my/9791/1/SHSAriffin2004_Efficient_accelerated_simulation_technique_for_packet.pdf Ariffin, Sharifah H. S. and Schormans, John A. (2004) Efficient accelerated simulation technique for packet switched networks : a buffer with two priority inputs. In: 2004 IEEE International Conference On Communications, Vols 1-7. IEEE, USA, pp. 2246-2250. ISBN 0-7803-8533-0 10.1109/ICC.2004.1312917 |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Ariffin, Sharifah H. S. Schormans, John A. Efficient accelerated simulation technique for packet switched networks : a buffer with two priority inputs |
| title | Efficient accelerated simulation technique for packet switched networks : a buffer with two priority inputs |
| title_full | Efficient accelerated simulation technique for packet switched networks : a buffer with two priority inputs |
| title_fullStr | Efficient accelerated simulation technique for packet switched networks : a buffer with two priority inputs |
| title_full_unstemmed | Efficient accelerated simulation technique for packet switched networks : a buffer with two priority inputs |
| title_short | Efficient accelerated simulation technique for packet switched networks : a buffer with two priority inputs |
| title_sort | efficient accelerated simulation technique for packet switched networks : a buffer with two priority inputs |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utm.my/9791/1/SHSAriffin2004_Efficient_accelerated_simulation_technique_for_packet.pdf http://eprints.utm.my/9791/ |
| url_provider | http://eprints.utm.my/ |