Scaling and numerical simulation analysis of 50 nm MOSFET incorporating dielectric pocket (DP-MOSFET)
Characterization of a metal-oxide-semiconductor field effect transistor (MOSFET)incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE) was demonstrated by using numerical simulation. The DP was incorporated between the channel and source/drain of planar MOSFET and was sca...
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Malaysian Solid State Science and Technology Society
2008
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| Online Access: | http://eprints.utm.my/8612/1/ZAFauzan2008-Scaling_And_Numerical_Simulation_Analysis.pdf http://eprints.utm.my/8612/ http://www.mass-malaysia.net/journal |
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| author | M. N., Zul Atfyi Fauzan Saad, Ismail Ismail, Razali |
| author_facet | M. N., Zul Atfyi Fauzan Saad, Ismail Ismail, Razali |
| author_sort | M. N., Zul Atfyi Fauzan |
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| content_provider | Universiti Teknologi Malaysia |
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| continent | Asia |
| country | Malaysia |
| description | Characterization of a metal-oxide-semiconductor field effect transistor (MOSFET)incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE) was demonstrated by using numerical simulation. The DP was incorporated between the channel and source/drain of planar MOSFET and was scaled to get an optimized structure. An analysis of current-voltage (I-V) of 50 nm channel length (Lg) has been
done successfully. The DP has suppressed short channel effect (SCE) without the needs of decreasing the junction depth. A reduction of leakage current (IOFF) was obtained in
MOSFET with DP without altering the drive current (ION). A very low leakage current is obtained for DP device with drain voltage (VDS) of 0.1 V and increase when VDS =
1.0 V. Consequently, the threshold voltage (VT) is increased accordingly with the increasing of body doping. A better control of VT roll-off was also demonstrated better
for MOSFET with DP as compared to conventional MOSFET. Thus, the incorporation of DP will enhance the electrical performance and give a very good control of the SCE
for scaling the MOSFET in nanometer regime for future development of nanoelectronics product. |
| format | Article |
| id | my.utm.eprints-8612 |
| institution | Universiti Teknologi Malaysia |
| language | en |
| publishDate | 2008 |
| publisher | Malaysian Solid State Science and Technology Society |
| record_format | eprints |
| spelling | my.utm.eprints-86122010-06-02T01:56:36Z http://eprints.utm.my/8612/ Scaling and numerical simulation analysis of 50 nm MOSFET incorporating dielectric pocket (DP-MOSFET) M. N., Zul Atfyi Fauzan Saad, Ismail Ismail, Razali TK Electrical engineering. Electronics Nuclear engineering Characterization of a metal-oxide-semiconductor field effect transistor (MOSFET)incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE) was demonstrated by using numerical simulation. The DP was incorporated between the channel and source/drain of planar MOSFET and was scaled to get an optimized structure. An analysis of current-voltage (I-V) of 50 nm channel length (Lg) has been done successfully. The DP has suppressed short channel effect (SCE) without the needs of decreasing the junction depth. A reduction of leakage current (IOFF) was obtained in MOSFET with DP without altering the drive current (ION). A very low leakage current is obtained for DP device with drain voltage (VDS) of 0.1 V and increase when VDS = 1.0 V. Consequently, the threshold voltage (VT) is increased accordingly with the increasing of body doping. A better control of VT roll-off was also demonstrated better for MOSFET with DP as compared to conventional MOSFET. Thus, the incorporation of DP will enhance the electrical performance and give a very good control of the SCE for scaling the MOSFET in nanometer regime for future development of nanoelectronics product. Malaysian Solid State Science and Technology Society 2008 Article PeerReviewed application/pdf en http://eprints.utm.my/8612/1/ZAFauzan2008-Scaling_And_Numerical_Simulation_Analysis.pdf M. N., Zul Atfyi Fauzan and Saad, Ismail and Ismail, Razali (2008) Scaling and numerical simulation analysis of 50 nm MOSFET incorporating dielectric pocket (DP-MOSFET). Journal of solid state science and technology, 16 (1). pp. 8-13. ISSN 0128-8393 http://www.mass-malaysia.net/journal |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering M. N., Zul Atfyi Fauzan Saad, Ismail Ismail, Razali Scaling and numerical simulation analysis of 50 nm MOSFET incorporating dielectric pocket (DP-MOSFET) |
| title | Scaling and numerical simulation analysis of 50 nm MOSFET incorporating dielectric pocket (DP-MOSFET)
|
| title_full | Scaling and numerical simulation analysis of 50 nm MOSFET incorporating dielectric pocket (DP-MOSFET)
|
| title_fullStr | Scaling and numerical simulation analysis of 50 nm MOSFET incorporating dielectric pocket (DP-MOSFET)
|
| title_full_unstemmed | Scaling and numerical simulation analysis of 50 nm MOSFET incorporating dielectric pocket (DP-MOSFET)
|
| title_short | Scaling and numerical simulation analysis of 50 nm MOSFET incorporating dielectric pocket (DP-MOSFET)
|
| title_sort | scaling and numerical simulation analysis of 50 nm mosfet incorporating dielectric pocket (dp-mosfet) |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utm.my/8612/1/ZAFauzan2008-Scaling_And_Numerical_Simulation_Analysis.pdf http://eprints.utm.my/8612/ http://www.mass-malaysia.net/journal |
| url_provider | http://eprints.utm.my/ |